mpc9850 Integrated Device Technology, mpc9850 Datasheet - Page 7

• Manufacturer Part Number: mpc9850
• Description: Xtal-input, Lvcmos Input, 8 Lvcmos Output Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9850
Clock Generator for PowerQUICC III
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 11. AC Characteristics (V
Input and Output Timing Specification
PLL Specifications
Skew and Jitter Specifications
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to V
3. In bypass mode, the MPC9850 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
t
reset_pulse
Symbol
t
t
t
JIT(PER)
reset_ref
f
t
f
t
JIT(CC)
t
t
f
f
refPW
refCcc
LOCK
JIT(∅)
t
sk(O)
sk(O)
VCO
MCX
DC
f
r
ref
, t
f
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode
VCO Frequency Range
Output Frequency
Reference Input Pulse Width
Input Frequency Accuracy
Output Rise/Fall Time
Output Duty Cycle
Maximum PLL Lock Time
MR Hold Time on Power Up
MR Hold Time
Output-to-Output Skew (within a bank)
Output-to-Output Skew (across banks A and B)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Generator
Generator
Z = 50Ω
Z = 50Ω
Pulse
Pulse
Characteristics
Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs)
DD
Figure 4. MPC9850 AC Test Reference (LVDS Outputs)
(4)
= 3.3 V ± 5%, V
Z
Z
V
O
O
V
TT
R
TT
= 50Ω
= 50Ω
R
T
T
= 50Ω
= 50Ω
Bank A output
Bank B output
Bank C output
DDOA
RMS (1 σ)
= 3.3 V ± 5%,V
(3)
DUT MPC9850
DUT MPC9850
TT
7
.
15.87
15.87
Min
150
50
43
47
10
10
2
DDOB
Z
Z
O
O
= 3.3 V ± 5%, T
R
= 50Ω
= 50Ω
2000
Typ
T
25
33
25
50
50
= 50Ω
R
T
= 100Ω
Max
250
200
200
500
100
500
400
200
150
200
57
53
10
50
50
V
A
TT
= –40°C to +85°C)
ref
= (f
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ppm
ms
ns
ps
ns
ns
ps
ps
ps
ps
ps
ps
%
VCO
÷ M) ⋅ N.
PLL bypass
PLL locked
20% to 80%
Bank A and B
Bank C
V
V
Bank A and B
Bank C
Bank A and C
Bank A and C
DDOA
DDOB
Condition
(1) (2)
= 3.3 V
= 3.3 V
MPC9850
NETCOM
MPC9850
7