sy89218u Micrel Semiconductor, sy89218u Datasheet - Page 4

• Manufacturer Part Number: sy89218u
• Description: Precision 1 15 Lvds Fanout Buffer With 2 1 Mux And Four ?1/?2/?4 Clock Divider Output Banks
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Pin Description
January 2007
20, 25, 30, 33,
41, 48, 50, 55,
Pin Number
34, 35,
38, 39,
44, 45,
15, 16
17, 18
11, 14
21, 22
23, 24
26, 27
28, 29
36, 37
42, 43
46, 47
51, 52
53, 54
56, 57
58, 59
60, 61
6, 12
5, 8,
1, 2
3, 4
13
10
40
62
31
7,
9
FSELA1, FSELA0
FSELB1, FSELB0
FSELC1, FSELC0
FSELD1, FSELD0
VREF-AC0,
VREF-AC1
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
/QA0, QA0
/QA1, QA1
/QB0, QB0
/QB1, QB1
/QB2, QB2
Pin Name
CLK_SEL
VT0, VT1
IN0, /IN0
IN1, /IN1
VCC
/MR
NC
Pin Function
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the
four banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open. The input-switching
threshold is V
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs
internally terminate to a VT pin through 50. Note that these inputs will default to an
indeterminate state if left open. Please refer to the “Input Interface Applications”
section for more details.
Input Termination Center-Tap: Each side of a differential input pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state
as long as /MR remains LOW. This input is internally connected to a 25k pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is
V
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs
to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is V
Positive Power Supply. Bypass with a 0.1F||0.01F low ESR capacitor as close to
V
Bank C LVDS differential output pairs controlled by FSELC1 and FSELC0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
No connect.
Bank D LVDS differential output pairs controlled by FSELD1 and FSELD0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
Bank A LVDS differential output pairs controlled by FSELA1 and FSELA0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
Bank B LVDS differential output pairs controlled by FSELB1 and FSELB0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
CC
CC
/2.
pin as possible.
CC
/2.
4
CC
–1.2V. They are used for AC-coupling
[e-mail]
or [phone]
M9999-012407-B
SY89218U
CC
/2.