sy89465u Micrel Semiconductor, sy89465u Datasheet - Page 4

• Manufacturer Part Number: sy89465u
• Description: Sy89465u Precision Lvds 1 10 Fanout With 2 1 Runt Pulse Eliminator Mux And Internal Termination
• Manufacturer: Micrel Semiconductor

Pin Description
Truth Table
December 2007
28, 33, 34, 41,
13, 15, 22, 23
Pin Number
1, 11, 6
43, 44
39, 40
37, 38
35, 36
31, 32
29, 30
26, 27
24, 25
20, 21
18, 19
16, 17
7, 10
2, 5
4, 9
3, 8
42
12
14
Exposed Pad
VREF-AC0
VREF-AC1
Pin Name
VT0, VT1
IN0, /IN0
IN1, /IN1
/Q0, Q0
/Q1, Q1
/Q2, Q2
/Q3, Q3
/Q4, Q4
/Q5, Q5
/Q6, Q6
/Q7, Q7
/Q8, Q8
/Q9, Q9
GND,
VCC
CAP
SEL
EN
IN0
X
X
0
1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV (200mV
pin of a pair internally terminates to a V
Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
inputs IN and /IN. Connect V
0.01µF low ESR capacitor to V
is only intended to drive its respective V
±1.5mA. Please refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to a
V
maximum interface flexibility. Please refer to the “Input Interface Applications” section
for more details.
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to
the V
Differential Outputs: These differential LVDS outputs are a logic function of the IN0,
IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state if left open. V
Ground: Ground and exposed pad must be connected to the same ground plane.
Power-On Reset (POR) initialization capacitor. When using the multiplexer with RPE
capability, this pin is tied to a capacitor to V
RPE logic starts up in a known state. See “Power-On Reset (POR) Description”
section for more details regarding capacitor selection. If this pin is tied directly to V
the RPE function will be disabled and the multiplexer will function as a normal
multiplexer. The CAP pin should never be left open or tied directly to GND.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9 outputs.
It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH
state if left open. When disabled, CLK output goes LOW and /CLK goes HIGH. EN
being synchronous, outputs will be enabled/disabled when they are in LOW state.
Thus, a runt pulse is avoided if the device is enabled/disabled by an asynchronous
control. V
T
/IN0
pin. The V
X
X
1
0
CC
pins as possible.
TH
Inputs
= V
IN1
X
X
T0
0
1
CC
and V
/2.
/IN1
T1
X
X
4
1
0
pins provide a center-tap to a termination network for
REF-AC
CC
SEL
0
0
1
1
TH
. Due to the limited drive capability, the V
directly to the corresponding V
= V
CC
T
T
pin through 50Ω. Please refer to the “Input
/2.
pin. Maximum sink/source current is
Q
0
1
0
1
Outputs
CC
CC
. The purpose is to ensure the internal
[e-mail]
–1.2V. They are used for AC-coupling
/Q
1
0
1
0
T
pin. Bypass with
M9999-120607-B
or [phone]
REF-AC
pp
). Each
pin
CC
,