APP750NP Agere Systems, APP750NP Datasheet - Page 2

• Manufacturer Part Number: APP750NP
• Description: 10G Network Processor Chip Set (APP750NP And APP750TM)
• Manufacturer: Agere Systems

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Features
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Product Brief
November 2002
Full line-rate performance with all packet sizes greater
than or equal to 40 bytes long
— Supports complex multifield packet classification with a
— Supports wire-speed access control list (ACL)
Multiprotocol customer-programmable classification:
— POS, MPLS, IPv4/v6, ATM, Frame Relay, Ethernet,
DRAM-based classification rule memory supports over
1 million IPv4 routes with separate information for each
VPN. No CAMs are required.
Uses high-level network processor programming
languages—Functional Programming Language (FPL) and
Agere Scripting Language (ASL)—preserving investments
in classification, policing, statistics, and packet modification
programming. FPL provides an order of magnitude
reduction (compared to C/C++) in the number of lines of
code required to specify packet classification policies. FPL
eliminates the need for complex hand-optimization of
assembly or microcode to achieve wire-speed
performance.
Programmable per-flow statistics and policing allows
OEMs to implement highly differentiated admission control
and billing policies.
Full carrier-class traffic management functionality to help
maximize the amount of premium traffic that can be reliably
served, with support for:
— Hierarchical weighted fair queuing (WFQ) with excellent
— VPNs with traffic isolation and service-level agreements
— Dynamic bandwidth and QoS/CoS modification to
— 2 million packet handling behavior types with 3 buffer
— Random early detection (RED) and weighted RED
— Up to 256 MB of external packet buffer memory per
VLANs, access control lists, link aggregation, etc. OEMs
can easily supplement the protocols and standards they
support with simple software upgrades.
large amount of headroom for future classification
needs.
processing, even with thousands of ACL rules.
direction
bandwidth and delay guarantees
(SLAs)
enable real-time dynamic service provisioning
management profiles per behavior type to allow fine-
grained service differentiation
(WRED)
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Applications
Target applications include multiprotocol core and edge
switches and routers, multiservice optical core and edge
devices and service-aware switches and provisioning
platforms.
— External scheduling port to allow OEMs to support
Programmable packet modification, including support for:
— Adding/removing software-defined headers and trailers
— Modifying data anywhere in the packet
— Forward congestion marking
Wire-speed IP fragmentation
Full multicast support with ability to individually schedule
and modify each packet/cell copy
Port based rate shaping for up to 256 media ports
— Configurations include OC192c, 4xOC48c, 1G/10G
PCI 2.2 compliant host interface to allow easy interfacing
to a variety of host microprocessors and other support
logic
Both cell- and frame-based fabrics supported with
programmable classification/segmentation/reassembly.
OEMs can readily interface to a wide variety of switch fab-
rics with minimal glue logic effort.
Support for simple interface to third-party fabrics using the
off-the-shelf FPGAs
Complete Agere Systems 10G fiber-to-fabric line card
reference design with supporting software
FPGA-based hardware emulation system and software
simulator provides complete pre-silicon hardware and
software development support.
Ethernet, 192xDS3, etc.
proprietary switch fabric implementations (for example,
credit-based flow control, global scheduling) and/or
proprietary packet scheduling implementations.
NP10 and TM 10 Network Processors