74hct7403 NXP Semiconductors, 74hct7403 Datasheet - Page 13

• Manufacturer Part Number: 74hct7403
• Description: 4-bit X 64-word Fifo Register; 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
With FIFO full; SI held HIGH in anticipation of empty location
Notes to Fig.7
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993
handbook, full pagewidth
4-Bit x 64-word FIFO register; 3-state
(1) HC : V
HCT: V
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
M
M
= 50%; V
= 1.3 V; V
I
= GND to V
I
SO INPUT
SI INPUT
DIR OUTPUT
= GND to 3 V.
CC
.
1
V M
(1)
2
V M
(1)
13
bubble - up
delay
t PLH
3
V M
(1)
t W
MGA660
4
5
74HC/HCT7403
Product specification