adf4206 Analog Devices, Inc., adf4206 Datasheet - Page 11

• Manufacturer Part Number: adf4206
• Description: Dual Rf Pll Frequency Synthesizers
• Manufacturer: Analog Devices, Inc.

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 22. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. Typical recommended external components are shown
in Figure 22.
RF INPUT STAGE
The RF input stage is shown in Figure 23. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
PRESCALER
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. Both RF1 and RF2 can be set to
either 32/33 or 64/65. DB20 of the AB counter latch selects the
value. See Figure 29 and Figure 31.
30pF
30pF
18kΩ
RF
RF
IN
IN
GENERATOR
A
B
OSC
OSC
Figure 22. Reference Input Stage
BIAS
OUT
IN
Figure 23. RF Input Stage
NC
POWER-DOWN
2kΩ
SW1
CONTROL
NO
1.6V
NC
SW2
SW3
2kΩ
100kΩ
AGND
AV
DD
BUFFER
TO R
COUNTER
Rev. A | Page 11 of 24
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The devices are guaranteed to work when the
prescaler output is 200 MHz or less.
PULSE SWALLOW FUNCTION
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
where:
f
P is the preset modulus of the dual modulus prescaler
B is the preset divide ratio of the binary 11-bit counter
A is the preset divide ratio of the binary 6-bit A counter
f
R is the preset divide ratio of the binary 14-bit programmable
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
VCO
REFIN
oscillator (VCO).
(32/33, 64/65).
(2 to 2047).
(0 to 63).
oscillator.
reference counter (1 to 16,383).
INPUT STAGE
is the output frequency of the external voltage controlled
f
is the output frequency of the external reference frequency
VCO
FROM RF
= [(P × B) + A] × f
N DIVIDER
MODULUS
CONTROL
N = BP + A
PRESCALER
Figure 24. A and B Counters
P/P + 1
REFIN
/R
ADF4206/ADF4208
LOAD
LOAD
COUNTER
COUNTER
11-BIT B
6-BIT A
TO PFD