mc145053p Lansdale Semiconductor, Inc., mc145053p Datasheet - Page 4

• Manufacturer Part Number: mc145053p
• Description: 10-bit A/d Converter With Serial Interface Cmos
• Manufacturer: Lansdale Semiconductor, Inc.

ML145053
Page 4 of 15
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
NOTES:
1, 4, 6 – 8
Figure
4, 7, 8
1. After the 10th SCLK falling edge (≥ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5 µs.
2. A CS edge may be received immediately after an active transition on the EOC pin.
1, 7
1, 7
2, 7
2, 7
6, 8
–
–
–
–
1
1
1
3
3
5
5
1
t PLH , t PHL
t PLZ , t PHZ
t PZL , t PZH
t TLH , t THL
Symbol
t CSd
t PHL
t CAs
C out
t wH
t r , t f
t wL
C in
t su
t su
t h
t h
t d
t h
f
Clock Frequency, SCLK
Note: Refer to t wH , t wL below
Minimum Clock High Time, SCLK
Minimum Clock Low Time, SCLK
Maximum Propagation Delay, SCLK to D out
Minimum Hold Time, SCLK to D out
Maximum Propagation Delay, CS to D out High-Z
Maximum Propagation Delay, CS to D out Driven
Minimum Setup Time, D in to SCLK
Minimum Hold Time, SCLK to D in
Maximum Delay Time, EOC to D out (MSB)
Minimum Setup Time, CS to SCLK
Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and
CS to Allow a Conversion
Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to
Abort a Conversion
Minimum Hold Time, Last SCLK to CS
Maximum Propagation Delay, 10th SCLK to EOC
Maximum Input Rise and Fall Times
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
Maximum Three-State Output Capacitance
www.lansdale.com
Parameter
(10- to 16-bit xfer) Max)
(11- to 16-bit xfer) Min
(10-bit xfer) Min
SCLK, CS, D in
AN0 – AN4
D in , CS
SCLK
D out
LANSDALE Semiconductor, Inc.
Guaranteed
Note 1
Note 2
2.425
Limit
2.35
190
190
125
150
100
100
300
2.1
2.3
10
10
55
15
15
0
0
9
0
1
MHz
Unit
ms
pF
pF
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
µs
ns
µs
µs
ns
Issue A