max5230beeet Maxim Integrated Products, Inc., max5230beeet Datasheet - Page 12

• Manufacturer Part Number: max5230beeet
• Description: 3v/5v, 12-bit, Serial Voltage-output Dual Dacs With Internal Reference
• Manufacturer: Maxim Integrated Products, Inc.

Table 1. Serial Data Format
The 3-wire serial interface (SPI, QSPI, MICROWIRE
compatible) used in the MAX5230/MAX5231 allows for
complete control of DAC operations (Figures 4 and 5).
Figures 1 and 2 show the timing for the serial interface.
The serial word consists of 3 control bits followed by 12
data bits (MSB first) and 1 sub-bit as described in
Tables 1, 2, and 3. When the 3 control bits are all zero
or all 1, D11–D8 are used as additional control bits,
allowing for greater DAC functionality.
The digital inputs allow any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC register(s) simultane-
Table 2. Serial-Interface Programming Commands
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
12
X = Don’t care.
* S0 must be zero for proper operation.
3 Control Bits
C2
0
0
0
1
1
1
1
0
0
0
0
0
0
0
C2…C0
______________________________________________________________________________________
MSB <------------16-bits of serial data ------------> LSB
C1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
C0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
MSB .. 12 Data Bits ... LSB
D11 ..............................D0
16-BIT SERIAL WORD
P1A P1B X X X X X X X X X X
0 1 1 P1A P1B X X X X X X X
1 1 0 P1A X X X X X X X X
1 1 1 P1B X X X X X X X X
X X X X X X X X X X X X
0 0 1 X X X X X X X X X
1 0 1 X X X X X X X X X
1 0 0 0 X X X X X X X X
1 0 0 1 X X X X X X X X
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
D11..............D0
Serial Interface
Sub-Bit
S0
S0*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Load input register A; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
Load all DAC registers from the shift register (start up both DACs
with new data, and load the input registers).
Update both DAC registers from their respective input registers (start
up both DACs with data previously stored in the input registers).
Load input register B; DAC registers are unchanged.
Load input register B; all DAC registers are updated.
Shut down both DACs, respectively, according to bits P1A and P1B
(see Table 3). Internal bias and reference remain active.
Update DAC register A from input register A (start up DAC A with
data previously stored in input register A).
Full Power-Down. Power down the main bias generator and shut
down both DACs, respectively, according to bits P1A and P1B (see
Table 3).
Update DAC register B from input register B (start up DAC B with
data previously stored in input register B).
Shut down DAC A according to bit P1A (see Table 3).
Shut down DAC B according to bit P1B (see Table 3).
Mode 0. DOUT clocked out on SCLK falling edge (default).
Mode 1. DOUT clocked out on SCLK rising edge.
ously. The control bits and D11–D8 allow the DACs to
operate independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with CS low during
this period. The control bits and D11–D8 determine
which registers update and the state of the registers
when exiting shutdown. The 3-bit control and D11–D8
determine the following:
• Registers to be updated
• Selection of the power-down and shutdown modes
The general timing diagram of Figure 1 illustrates data
acquisition. Driving CS low enables the device to
receive data. Otherwise the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the control bits and D11–D8. The maxi-
mum clock frequency guaranteed for proper operation
is 13.5MHz. Figure 2 depicts a more detailed timing
diagram of the serial interface.
FUNCTION