maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet
maxq3180-ran
Available stocks
Related parts for maxq3180-ran
maxq3180-ran Summary of contents
Page 1
... Power-Fail Detection o Bidirectional Reset Input/Output o SPI-Compatible Serial Interface with Interrupt Request (IRQ) Output o Single 3.3V Supply, Low Power (10mW Typical) o 28-Pin TSSOP Package PART MAXQ3180-RAN+ +Denotes a Pb-free/RoHS-compliant package. Pin Configuration and Typical Application Circuit appear at end of data sheet. Ordering Information PIN- TEMP RANGE PACKAGE -40° ...
Page 2
Low-Power, Multifunction, Polyphase AFE ABSOLUTE MAXIMUM RATINGS Voltage Range on DVDD Relative to DGND .........-0.3V to +4.0V Voltage Range on AVDD Relative to AGND..........-0.3V to +4.0V Voltage Range on AGND Relative to DGND ..........0.3V to +0.3V Voltage Range on AVDD ...
Page 3
Low-Power, Multifunction, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued) ( 3.6V -40°C to +85°C, unless otherwise noted.) (Note RST A PARAMETER SYMBOL DIGITAL I/O SPECIFICATIONS Input High Voltage Input Low Voltage Input ...
Page 4
Low-Power, Multifunction, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued) ( 3.6V -40°C to +85°C, unless otherwise noted.) (Note RST A PARAMETER SYMBOL SPI SLAVE-MODE INTERFACE TIMING SCLK Input Pulse-Width High SCLK Input ...
Page 5
... I2N VN RESET MULTIPLY 48-BIT ACCUMULATE _______________________________________________________________________________________ REF ADC ADC CONTROL, ELECTRICITY METERING DSP, COMMUNICATIONS MANAGER WATCHDOG TIMER POR/ BROWNOUT SYSCLK MONITOR ADCCLK MAXQ3180 Block Diagram CFP, CFQ COUNTERS I/O BUFFERS I/O REGISTERS SPI I/O BUFFERS I/O REGISTERS I/O I/O REGISTERS BUFFERS HF RC OSC/8 HF ADC CLOCK ...
Page 6
... Master Out-Slave In Input. This line is used by the master to transmit data to the slave (the 15 MOSI MAXQ3180) over the SPI interface. Master In-Slave Out Output. This line is used by the MAXQ3180 (the slave) to transmit data back to 16 MISO the master over the SPI interface. ...
Page 7
... Power Measurement Mode (LPMM). In this mode, no power measurements are taken because the MAXQ3180 has not yet been configured. When entering this mode, the MAXQ3180 sets the status flag NOINIT to 1 and drives the IRQ pin low to indicate to the master that initialization is required. The master is responsible for performing the following series of operations: • ...
Page 8
... MAXQ3180 automatically resumes electric-metering functions and sample processing. Note that when the master is communicating with the MAXQ3180, the SSEL line is normally driven low at the beginning of each SPI command. This means that if the master sends an SPI command after the MAXQ3180 enters Stop Mode, the MAXQ3180 automatically exits Stop Mode and receives the command ...
Page 9
... Low-Power, Multifunction, Polyphase AFE There are several different sources that can cause the MAXQ3180 to undergo a reset cycle. For any type of hardware reset, the RESET pin is driven low when a reset occurs. This hardware reset is initiated by an external source (such as the master controller or a manual pushbutton press) driving the RESET pin on the MAXQ3180 low ...
Page 10
... INTERNAL RESET STOP MODE Figure 3. Brownout Reset error of some kind causes the MAXQ3180 to lock up or enter an endless execution loop, the watchdog timer expires and triggers an automatic hardware reset. There is no register flag to indicate to the master that a watch- dog reset has occurred, but the RESET line strobes low briefly ...
Page 11
... This clock can be obtained from any one of three selec- table sources, as shown in Figure 4. External High-Frequency Crystal The default system clock source for the MAXQ3180 is an external high-frequency crystal oscillator circuit con- nected between XTAL1 and XTAL2. When clocked with an external crystal, a parallel-resonant, AT-cut crystal oscillating in the fundamental mode is required ...
Page 12
... XTAL2 pin should be left uncon- nected. The master should also shut down the internal crystal oscillator circuit by setting the EXTCLK bit (STA- TUS0. This bit is only cleared by the MAXQ3180 if a power-on or brownout reset occurs and is unaffect other resets. ...
Page 13
... Transfers over the SPI interface always start with the most significant bit and end with the least significant bit. All SPI data transfers to and from the MAXQ3180 are always 8 bits (one byte) in length. The MAXQ3180 SPI interface does not support 16-bit character lengths. ...
Page 14
... MAXQ3180’s clock frequency divided by 8. For example, when the MAXQ3180 is run- ning at 8MHz, the SPI clock frequency must be 1MHz or less. And if the MAXQ3180 is running in LPMM Mode (or if the crystal is still warming up), the SPI clock fre- quency must remain at 125kHz or less for proper com- munications operation ...
Page 15
Low-Power, Multifunction, Polyphase AFE Table 1. Command Format for SPI Register Read BYTE TRANSFERS Master sends command; 1st byte Slave sends 0xC1 byte Master sends address; 2nd byte Slave sends 0xC2 byte Master sends dummy; Sync bytes Slave sends ACK ...
Page 16
... Optionally, a cyclic redundancy check (CRC) byte can be appended to each transaction. For write commands, the CRC byte is sent by the master, and for read com- mands the CRC byte is sent by the MAXQ3180. The CRC mode is enabled when the CRCEN bit is set STATUS0 register. Otherwise, the MAXQ3180 assumes no CRC byte is used ...
Page 17
Low-Power, Multifunction, Polyphase AFE Table 3. RAM Register Map x0h x1h x2h x3h 0xh STATUS0 OPMODE 1xh SCAN_0 SCAN_1 2xh TIME_FS VOLT_FS 3xh CYCNT PLSCFG 4xh 5xh 6xh BPF_B0F BPF_A1F 7xh OCLVL OVLVL 8xh COM_TIMO R_ACFG 9xh RAW_TEMP Axh Bxh ...
Page 18
Low-Power, Multifunction, Polyphase AFE Table 3. RAM Register Map (continued) x0h x1h x2h x3h 21xh 22xh 23xh 24xh 25xh 26xh 27xh 28xh PHASE_B_IRMS PHASE_B_ 29xh PHASE_B_REA ACT 2Axh 2Bxh PHASE_C_ PHASE_C_ 2Cxh KWHAP KWHAN PHASE_C_ PHASE_C_ 2Dxh I_GAIN V_GAIN PHASE_C_ ...
Page 19
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary ADDRESS NAME DESCRIPTION (BYTE) 0 STATUS0 Status 0x000 2 Mode of OPMODE 0x002 Operation Status. Device drives IRQ low when 4 STATUS1 0x004 any bit in this register is set and ...
Page 20
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) 8 STATUS2 Status 0x008 Connection and 10 Power CONNCT 0x00A Calculation Configuration RESERVED 12–15 — Analog Scan SCAN_0 16 Configuration (Slot 0) 20 ______________________________________________________________________________________ DEFAULT R/W ...
Page 21
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) Analog Scan SCAN_0 16 Configuration (Slot 0) Analog Scan 18 Configuration SCAN_1 0x012 (Slot 1) Analog Scan 20 SCAN_2 Configuration 0x014 (Slot 2) Analog Scan 22 ...
Page 22
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) 38 Power PWR_FS 0x026 Calibration 40 KWHT kWh Threshold 0x028 44 KAHT kAh Threshold 0x02C 48 CYCNT Cycle Count 0x030 50 Pulse Output PLSCFG 0x032 Configuration ...
Page 23
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) LPF Coefficient 90 LPF_B0FNS for NS 0x05A Calculation LPF Coefficient 92 for Samples LPF_B0FSM 0x05C Calculation 94 HPF_B0F HPF Coefficient 0x05E 96 BPF and BSF BPF_B0F ...
Page 24
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) Reverse Pulse 124 REV_TIMO Direction 0x07C Timeout Energy 126 ACC_TIMO Accumulation 0x07E Delay Timeout 128 Communication COM_TIMO 0x080 Timeout 130 Analog Control R_ACFG 0x082 Shadow 132 ...
Page 25
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) 138 No-Load NOLOAD 0x08A Threshold 140 Raw Line-Cycle NS 0x08C Period 144 Temperature RAW_TEMP 0x090 Sample RESERVED 146–223 — PHASE_A_ 224 Active Positive KWHAP 0x0E0 Energy ...
Page 26
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) Linearity PHASE_A_ 246 Coefficient: EOFF_HI 0x0F6 High Range Energy Offset Linearity PHASE_A_E 248 Coefficient: _GAIN_LO 0x0F8 Low Range Energy Gain Linearity PHASE_A_ 250 Coefficient: EOFF_LO 0x0FA ...
Page 27
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_A_ 264 Current Peak IPK 0x108 PHASE_A_ 266 Voltage Peak VPK 0x10A RESERVED 268–401 — PHASE_A_ 402 Raw RMS IRMS 0x192 Current PHASE_A_ 406 Raw RMS ...
Page 28
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_B_ 478 Amp-Hours KWHIH 0x1DE PHASE_B_ 480 Current Gain I_GAIN 0x1E0 Coefficient PHASE_B_ 482 Voltage Gain V_GAIN 0x1E2 Coefficient Power and PHASE_B_ 484 Energy Gain E_GAIN_HI ...
Page 29
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_B_ 500 Interrupt Flags FLAGS PHASE_B_ Energy Overflow 502 EOVFL Flags PHASE_B_ 504 Current Peak IPK PHASE_B_ 506 Voltage Peak VPK RESERVED 508–641 — PHASE_B_ Raw ...
Page 30
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_C_ Reactive Q1 708 KWHR1 Energy PHASE_C_ Reactive Q2 710 KWHR2 Energy PHASE_C_ Reactive Q3 712 KWHR3 Energy PHASE_C_ Reactive Q4 714 KWHR4 Energy PHASE_C_ 716 ...
Page 31
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_C_ Phase Angle 732 PA_0 Coefficient PHASE_C_ Phase Angle 734 PA_1 Coefficient PHASE_C_ Phase Angle 736 PA_2 Coefficient PHASE_C_ Phase Angle 738 PA_3 Coefficient PHASE_C_ 740 ...
Page 32
Low-Power, Multifunction, Polyphase AFE Table 4. RAM Register Summary (continued) ADDRESS NAME DESCRIPTION (BYTE) PHASE_C_ Raw Active 894 ACT Energy PHASE_C_ Raw Reactive 898 REA Energy PHASE_C_ Raw Apparent 902 APP Energy RESERVED 906–943 — NEUTRAL_ 944 Amp-Hours KWHIH NEUTRAL_I ...
Page 33
... All reads from these registers return dummy data. Analog Front-End Processing Whenever the MAXQ3180 is in one of the active operat- ing modes (Run Mode or LPMM Mode), the analog front-end operates continuously, scanning through up to eight scan slots depending on the selected front-end configuration ...
Page 34
... Following the LPF filter processing stage, the MAXQ3180 scans the voltage signals to detect ascend- ing zero-crossing events for each voltage phase. For each phase A, B, and C, the MAXQ3180 counts the number of scan frames (NS) between two consecutive zero crossings. The global value, common for all three phases, and is located in RAM at address 0x08C ...
Page 35
... If no ascending zero crossings are detected within a specified number of analog scan frame periods, the NOZC (STATUS1.11) flag is set by the MAXQ3180 to notify the master of this condition. If the interrupt enable bit INT_MASK.11 is set to 1, the interrupt signal IRQ is driven low by the MAXQ3180 whenever NOZC = 1 ...
Page 36
... NS is the number of samples per line cycle (fac- tor approximately 16 for 50Hz signal and 200µs sam- pling rate). The output of the integrator is scaled down by factor 16 in the MAXQ3180. The HPF, when combined with the digital integrator, introduces an additional phase shift into the current ...
Page 37
... Curve-fitting coefficients are usually obtained during the calibration process and loaded into RAM registers upon initialization. Once the phase angle PA has been calcu- lated, the MAXQ3180 calculates SIN(PA) and COS(PA) and performs phase compensation for active and reac- tive energy. By default, all curve-fitting coefficients are zeros: PA_0 = PA_1 = PA_2 = PA_3 = 0 ...
Page 38
... Energy Pulse Output The two pulse output pins, CFP and CFQ, have associ- ated accumulators PLS1, PLS2 and configurable thresholds THR1, THR2. The MAXQ3180 issues a pulse on the output pin when the pulse accumulator exceeds the threshold level (e.g., PLS1 > THR1), then continues accumulation from the level PLS1 = PLS1 - THR1 ...
Page 39
... Other Peak Voltage and Current Detection The MAXQ3180 records peak current and voltage lev- els for phase A, phase B, and phase C as follows. The peak RMS values of the current and voltage within a fixed number of accumulation cycles are stored in the IPK and VPK registers for each phase. The values stored in IPK and VPK represent only the 16 most sig- nificant bits of the raw RMS registers, i ...
Page 40
... Low-Power, Multifunction, Polyphase AFE MAXQ3180 never clears them on its own unless a reset occurs. The interrupt flags should be cleared by the master by writing the appropriate register. The configuration bits OVEN and OCEN allow enable- or disable-monitoring the overvoltage and overcurrent events on each phase independently. ...
Page 41
Low-Power, Multifunction, Polyphase AFE Table 12. Meter Unit Definitions REGISTER OR RAM ADDRESS ACCUMULATOR (BYTE) 402, 642, 882, Raw IRMS Sample 996 Raw VRMS Sample 406, 646, 886 410, 650, 890, Raw IH Sample 1000 414, 418, 422, Raw Act, ...
Page 42
... To activate tempera- ture measurement, the master must write one of the TMPC[1:0] bits in the OPMODE register. When TMPC0 is set to 1, the MAXQ3180 performs a single tempera- ture conversion by forcing bias currents 1µA and 16µA through a pair of diode stacks, placing the result in the RAW_TEMP register and automatically clearing the TMPC0 bit to 0 ...
Page 43
... Measure the power output of the meter. This can be done in two ways: (a) by reading raw RAM reg- 30 isters from the MAXQ3180, or (b) by measuring pulse output error. The following procedure depends on the way of measuring power output. a) Measure average raw apparent energy by reading the RAM register several times. ...
Page 44
... Low-Power, Multifunction, Polyphase AFE the Voltage Gain Calibration section, and t the sampling time that depends on the MAXQ3180 system clock frequency and sam- pling rate register setting (ADCRATE (ADCRATE + 1) x 8/f FR For example, for the default conditions ADCRATE = 199 and f SYS 200µs = 55.55nh. Using typical example values ...
Page 45
... Phase Angle Calibration This calibration is intended to compensate for phase angle errors across the range of input loads. The MAXQ3180 uses four PA_n coefficients to calculate the compensation phase angle as a 3rd-order polynomial: compensation_phase_angle = PA_0 + (PA_1 (PA_2 x X Where X is proportional to the logarithm of raw IRMS. ...
Page 46
... MATLAB from Because the MAXQ3180 is designed for use in systems where high voltages are present, care must be taken to route all signal paths, both analog and digital, as far away as possible from the high-voltage components possible to construct more elaborate metering designs using multiple MAXQ3180 devices ...
Page 47
... Low-Power, Multifunction, Polyphase AFE VOLTAGE SENSE CURRENT TRANSFORMER ______________________________________________________________________________________ Typical Application Circuit R1 V0P R2 R1 V1P R2 MAXQ3180 R1 V2P R2 VCOMM VN I0P R3 R3 I0N I1P R3 R3 I1N I2P R3 R3 I2N MASTER 47 ...
Page 48
... Low-Power, Multifunction, Polyphase AFE Pin Configuration TOP VIEW VN 1 INP 2 I0P 3 I0N 4 I1P 5 I1N 6 I2P 7 MAXQ3180 I2N 8 AGND 9 XTAL2 10 XTAL1 11 IRQ 12 SSEL 13 SCLK 14 TSSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...