maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet - Page 12

• Manufacturer Part Number: maxq3180-ran
• Description: Low-power, Multifunction, Polyphase Afe
• Manufacturer: Maxim Integrated Products, Inc.

clock input and the XTAL2 pin should be left uncon-
nected. The master should also shut down the internal
crystal oscillator circuit by setting the EXTCLK bit (STA-
TUS0.6) to 1. This bit is only cleared by the MAXQ3180
if a power-on or brownout reset occurs and is unaffect-
ed by other resets.
When using an external high-frequency clock, the clock
signal should be generated by a CMOS driver. If the
clock driver is a TTL gate, its output must be connected
to DVDD through a pullup resistor to ensure that the
correct logic levels are generated. To minimize system
noise in the clock circuitry, the external clock source
must meet the maximum rise and fall times and the
minimum high and low times specified for the clock
source in the Electrical Characteristics table.
When the external high-frequency crystal is warming
up, or when the MAXQ3180 is placed into LPMM mode,
the system clock is sourced from an internal RC oscilla-
tor. This internal oscillator is designed to run at approxi-
mately 8MHz, although the exact frequency varies over
temperature and supply voltage.
If no external crystal circuit or high-frequency clock will
be used, the MAXQ3180 can be forced to operate
indefinitely from the internal oscillator by grounding
XTAL1. This ensures that the crystal warmup count
never completes, so the MAXQ3180 runs from the inter-
nal oscillator in all active modes (Initialization Mode,
Run Mode, and LPMM Mode).
Before the MAXQ3180 can begin performing electric-
metering operations, the master must initialize a num-
ber of configuration parameters. Since the MAXQ3180
does not contain internal nonvolatile memory, these
parameters (stored in internal registers) must be set by
the master each time a power-up or reset cycle occurs,
or each time a switch is made between LPMM Mode
and Run Mode.
The external master communicates with the MAXQ3180
over a standard SPI bus, using commands to read and
write values to internal registers on the MAXQ3180.
These registers include, among many other items:
• Operating mode settings (Stop Mode, LPMM Mode,
• Status and interrupt flags (not initialized, power-sup-
• Masking control for interrupts to determine which
• Configuration settings for analog channel scanning
Low-Power, Multifunction, Polyphase AFE
12
external clock mode, etc.)
ply failure, overcurrent/overvoltage detection)
conditions cause IRQ to be driven low
______________________________________________________________________________________
Master Communications
Internal RC Oscillator
• Power pulse output configuration
• Filter coefficients and configuration
• Read-only registers containing accumulated power
Once all the configuration registers have been set by
the master to their proper values, the master must clear
the NOINIT flag (STATUS1.0) to zero. Once this flag has
been cleared, the MAXQ3180 exits Initialization Mode
and begins execution in either Run Mode or LPMM
Mode, depending on the setting of the LOWPM bit.
As the MAXQ3180 obtains voltage and current mea-
surements in Run Mode or LPMM Mode, it accumu-
lates, filters, and performs a number of calculations on
the collected data. Many of these operations (including
the various filtering stages) are configured by settings
in registers written by the master. The output results
can then be read by the master from various read-only
registers in parallel with the ongoing measurement and
processing operations.
The MAXQ3180 provides an SPI bus for master/slave
communications. All communications transfers are initi-
ated by the external master. The interrupt request line
IRQ, while not technically part of the SPI bus interface,
is also used for master/slave communications, since it
allows the MAXQ3180 to notify the master that an inter-
rupt condition exists.
During an SPI transfer, data is simultaneously transmit-
ted and received over two serial data lines (MISO and
MOSI) with respect to a single serial shift clock (SCLK).
The polarity and phase of the serial shift clock are the
primary components in defining the SPI data transfer
format. The polarity of the serial clock corresponds to
the idle logic state of the clock line and, therefore, also
defines which clock edge is the active edge. To define
a serial shift clock signal that idles in a logic-low state
(active clock edge = rising), the clock polarity select
(CKPOL; SPICF.0) bit should be configured to a 0,
while setting CKPOL = 1 causes the shift clock to idle
in a logic-high state (active clock edge = falling). The
phase of the serial clock selects which edge is used to
sample the serial shift data. The clock phase select
(CKPHA; SPICF.1) bit controls whether the active or
inactive clock edge is used to latch the data. When
CKPHA is set to a logic 1, data is sampled on the inac-
tive clock edge (clock returning to the idle state). When
CKPHA is set to a logic 0, data is sampled on the
active clock edge (clock transition to the active state).
Together, the CKPOL and CKPHA bits allow four possi-
ble SPI data transfer formats.
and energy data
SPI Communications Rate and Format