adc08d1010diyb National Semiconductor Corporation, adc08d1010diyb Datasheet
adc08d1010diyb
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adc08d1010diyb Summary of contents
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... Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus- ≤ ≤ trial (-40°C T +85°C) temperature range. A © 2008 National Semiconductor Corporation Features ■ Internal Sample-and-Hold ■ Single +1.9V ±0.1V Operation ■ Choice of SDR or DDR output clocking ■ ...
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Block Diagram www.national.com 2 20146753 ...
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... Ordering Information Industrial Temperature Range (-40°C < T < +85°C) A ADC08D1010DIYB Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. NS Package 128-Pin Exposed Pad LQFP 3 20146701 www.national.com ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 3 OutV / SCLK OutEdge / DDR / 4 SDATA 15 DCLK_RST CAL 29 PDQ 14 FSR/ECE www.national.com Equivalent Circuit Output Voltage Amplitude and Serial Interface Clock. ...
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Pin Functions Pin No. Symbol Equivalent Circuit CalDly / DES / 127 SCS 18 CLK+ 19 CLK I− Q− CMO V 31 ...
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Pin Functions Pin No. Symbol R 32 EXT 34 Tdiode_P 35 Tdiode_N DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− ...
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Pin Functions Pin No. Symbol Equivalent Circuit 13, 16, 17, 20 25, 28, 33, 128 40, 51 ,62, 73, 88, 99 110, 121 12, 21, 24, 27, GND 41 42, ...
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Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Input Pin Ground Difference |GND ...
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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) INTERLEAVE MODE (DES ...
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Symbol Parameter R Differential Input Resistance IN ANALOG OUTPUT CHARACTERISTICS V Common Mode Output Voltage CMO V input threshold to set DC CMO V CMO_LVL Coupling mode Common Mode Output Voltage TC V CMO Temperature Coefficient Maximum V load CMO ...
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Symbol Parameter Output Offset Voltage, see Figure Output Offset Voltage, see Figure Output Offset Voltage Change Δ Between Logic Levels I Output Short Circuit Current OS Z Differential Output Impedance O V ...
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Symbol Parameter t Sampling (Aperture) Delay AD t Aperture Jitter AJ Input Clock to Data Output Delay t OD (in addition to Pipeline Delay) Pipeline Delay (Latency) (Notes 11, 14) Over Range Recovery Time PD low to Rated Accuracy t ...
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Note 7: To guarantee accuracy required that V achieving rated performance requires that the backside exposed pad be well grounded. Note 8: Typical figures are 25°C, and represent most likely parametric norms. Test limits are ...
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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one- half the sampling frequency, ...
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Timing Diagrams www.national.com FIGURE 3. ADC08D1010 Timing — SDR Clocking FIGURE 4. ADC08D1010 Timing — DDR Clocking 16 20146714 20146759 ...
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FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low 17 20146719 20146720 20146723 www.national.com ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing www.national.com 18 20146724 20146725 ...
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Typical Performance Characteristics INL vs. CODE DNL vs. CODE POWER DISSIPATION vs. SAMPLE RATE V =V =1.9V, F =1000MHz CLK INL vs. TEMPERATURE 20146764 DNL vs. TEMPERATURE 20146766 ENOB vs. CLOCK DUTY CYCLE 20146781 19 =25°C unless ...
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ENOB vs. TEMPERATURE ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE www.national.com ENOB vs. SUPPLY VOLTAGE 20146776 ENOB vs. INPUT FREQUENCY 20146778 SNR vs. SUPPLY VOLTAGE 20146768 20 20146777 20146779 20146769 ...
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SNR vs. SAMPLE RATE 20146770 THD vs. TEMPERATURE 20146772 THD vs. SAMPLE RATE 20146774 SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY 21 20146771 20146773 20146775 www.national.com ...
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SFDR vs. TEMPERATURE SFDR vs. SAMPLE RATE CROSSTALK vs. SOURCE FREQUENCY www.national.com SFDR vs. SUPPLY VOLTAGE 20146785 SFDR vs. INPUT FREQUENCY 20146782 FULL POWER BANDWIDTH 20146763 22 20146784 20146783 20146786 ...
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Functional Description The ADC08D1010 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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It is important that the input signals are either a.c. coupled to the inputs with the V pin grounded, or d.c. coupled with CMO the V pin left floating. An input common mode voltage CMO equal to the V ...
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If the LVDS lines are long and/or the system in which the ADC08D1010 is used is noisy, it may be necessary to tie the OutV pin high. The LVDS data output have a typical common mode voltage of ...
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The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device) and is shown in Table 3. TABLE 3. Extended Control Mode Operation (Pin 14 Floating) Extended Control Mode Feature SDR or DDR ...
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Bit 10 nDE: DDR Enable. When this bit is set to 0b, data bus clocking follows the DDR (Dual Data Rate) mode whereby a data word is output with each rising and falling edge of DCLK. When this bit is ...
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Q-Channel Full-Scale Voltage Adjust Addr: Bh (1011b) D15 D14 D13 D12 D11 (MSB Adjust Value ) (LSB Bit 15:7 Full Scale Voltage Adjust Value. The input full- scale voltage or ...
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DES Fine Adjust Addr: Fh (1111b) D15 D14 D13 D12 D11 D10 (MSB) FAM (LSB Bits 15:7 Fine Adjust Magnitude. Each code value in this field delays either the "I" ...
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TABLE 5. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP (Non-Extended Control Mode, FSR High − − 217.5mV V + 217.5mV − 109 109 ...
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Handling Single-Ended Input Signals There is no provision for the ADC08D1010 to adequately pro- cess single-ended input signals. The best way to handle single-ended signals is to convert them to differential signals before presenting them to the ADC. The ...
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CONTROL PINS Six control pins (without the use of the serial interface) provide a wide range of possibilities in the operation of the AD- C08D1010 and facilitate its use. These control pins provide Full-Scale Input Range setting, Self Calibration, ...
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The Calibration Delay will then only be a short delay. In the enhanced control mode, either input may be used for dual edge sampling. See Section 1.1.5.1. IMPORTANT NOTES : 1) For the Extended Control Mode ...
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FIGURE 15. Non-Spiking Power Supply The output drivers should have a supply voltage, V within the range specified in the Operating Ratings table. This voltage should not exceed the V supply voltage the power is applied to the ...
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The solution is to keep the analog cir- cuitry well separated from the digital circuitry. High power digital components should not be located on or near any linear component or power supply trace or plane that services ...
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Driving the V pin to change the reference voltage mentioned in Section 2.1, the reference voltage is intended to be fixed to provide one of two different full-scale values (650 mV and 870 mV ). Over driving this ...
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... Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP Order Number ADC08D1010DIYB NS Package Number VNX128A 37 www.national.com ...
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