adc12041 National Semiconductor Corporation, adc12041 Datasheet - Page 22

• Manufacturer Part Number: adc12041
• Description: 12-bit Plus Sign 216 Khz Sampling Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Features and Operating Modes
DIGITAL INTERFACE
The digital control signals are CS, RD, WR and RDY. Spe-
cific timing relationships are associated with the interaction
of these signals. Refer to the Digital Timing Diagrams sec-
tion for detailed timing specifications. The active low RDY
signal indicates when a certain event begins and ends. It is
recommended that the ADC12041 should only be accessed
when the RDY signal is low. It is in this state that the
ADC12041 is ready to accept a new command. This will
minimize the effect of noise generated by a switching data
bus on the ADC. The only exception to this is when the
ADC12041 is in the standby mode at which time the RDY is
high. The ADC12041 is in the standby mode at power up or
when a STANDBY command is issued. A Ful-Cal, Auto-Zero,
Reset or Start command will get the ADC12041 out of the
standby mode. This may be observed by monitoring the sta-
tus of the RDY signal. The RDY signal will go low when the
ADC12041 leaves the standby mode.
The following describes the state of the digital control signals
for each programmed event in both 8-bit and 13-bit mode.
RDY should be low before each command is issued except
for the case when the device is in standby mode.
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode: A Ful-Cal or Auto-Zero command must be issued
and the BW bit (b
pulse on the WR pin will force the RDY signal high. At this
time the converter begins executing a full calibration or
auto-zero cycle. The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done.
13-bit mode: A Ful-Cal or Auto-Zero command must be is-
sued and the BW bit (b
pulse on the WR pin will force the RDY signal high. At this
time the converter begins executing a full calibration or
auto-zero cycle. The RDY signal will automatically go low
when the full calibration or auto-zero cycle is done.
STARTING A CONVERSION: START COMMAND
In order to completely describe the events associated with
the Start command, both the SYNC-OUT and SYNC-IN
modes must be considered.
SYNC-OUT/Asynchronous
8-bit mode: A write to the ADC12041 should set the acquisi-
tion time, clear the BW and SYNC bit and select the START
command in the Configuration register. In order to initiate a
conversion, two reads must be performed from the
ADC12041. The rising edge of the second read pulse will
force the RDY pin high and begin the programmed acquisi-
tion time selected by bits b
ister. The SYNC pin will go high indicating that a conversion
sequence has begun following the end of the acquisition pe-
riod. The RDY and SYNC signal will fall low when the con-
version is done. At this time new information, such as a new
acquisition time and operational command can be written
into the Configuration register or it can remain unchanged.
Assuming that the START command is in the Configuration
register, the previous conversion can be read. The first read
places the lower byte of the conversion result contained in
the Data register on the data bus. The second read will place
the upper byte of the conversion result stored in the Data
register on the data bus. The rising edge on the second read
pulse will begin another conversion sequence and raise the
RDY and SYNC signals appropriately.
(Continued)
3
) cleared. The active edge of the write
3
) set. The active edge of the write
1
and b
0
of the Configuration reg-
22
13-bit mode: The acquisition time should be set, the BW bit
set, the SYNC bit cleared and the START command issued
with a write to the ADC12041. In order to initiate a conver-
sion, a single read must be performed from the ADC12041.
The rising edge of the read signal will force the RDY signal
high and begin the programmed acquisition time selected by
bits b
go high indicating that a conversion sequence has begun fol-
lowing the end of the acquisition period. The RDY and SYNC
signal will fall low when the conversion is done. At this time
new information, such as a new acquisition time and opera-
tional command can be written into the Configuration regis-
ter or it can remain unchanged. With the START command in
the Configuration register, a read from the ADC12041 will
place the entire 13-bit conversion result stored in the data
register on the data bus. The rising edge of the read pulse
will immediately force the RDY output high and begin the
programmed acquisition time selected by bits b
the configuration register. The SYNC will then go high at the
end of the programmed acquisition time.
SYNC-IN/Synchronous
For the SYNC-IN case, it is assumed that a series of SYNC
pulses at the desired sampling rate are applied at the SYNC
pin of the ADC12041.
8-bit mode: A write to the ADC12041 should set the SYNC
bit, write the START command and clear the BW bit. The
programmed acquisition time in bits b
condition in the SYNC-IN mode.
A rising edge on the SYNC pin or the second rising edge of
two consecutive reads from the ADC12041 will force the
RDY signal high. It is recommended that the action of read-
ing from the ADC12041 (not the rising edge of the SYNC sig-
nal) be used to raise the RDY signal. This will ensure that the
conversion result is read during the acquisition period of the
next conversion cycle, eliminating a read from the
ADC12041 while it is performing a conversion. Noise gener-
ated by accessing the ADC12041 while it is converting may
degrade the conversion result. In the SYNC-IN mode, only
the rising edge of the SYNC signal will begin a conversion
cycle. The rising edge of the SYNC also ends the acquisition
period. The acquisition period begins after the falling edge of
the RDY signal. The input is sampled until the rising edge of
the SYNC pulse, at which time the signal will be held and
conversion begins. The RDY signal will go low when the con-
version is done and a new operational command may be
written into the Configuration register at this time, if needed.
Two consecutive read cycles are required to retrieve the en-
tire 13-bit conversion result from the ADC12041’s Data reg-
ister. The first read will place the lower byte of the conversion
result contained in the Data register on the data bus. The
second read will place the upper byte of the conversion re-
sult stored in the Data register on the data bus. With the
START command in the configuration register, the rising
edge of the second read pulse will raise the RDY signal high
and begin a conversion cycle following a rising edge on the
SYNC pin.
13-bit mode: The SYNC bit and the BW bit should be set and
the START command issued with a write to the ADC12041.
A rising edge on the SYNC pin or on the RD pin will force the
RDY signal high. It is recommended that the action of read-
ing from the ADC12041 (not the rising edge of the SYNC sig-
nal) be used to raise the RDY signal. This will ensure that the
conversion result is read during the acquisition period of the
next conversion cycle, eliminating a read from the
ADC12041 while it is performing a conversion. Noise gener-
ated by accessing the ADC12041 while it is converting may
1
and b
0
of the configuration register. The SYNC pin will
1
and b
0
is a don’t care
1
and b
0
of