adc12041 National Semiconductor Corporation, adc12041 Datasheet - Page 7

• Manufacturer Part Number: adc12041
• Description: 12-bit Plus Sign 216 Khz Sampling Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

t
t
t
t
RDRDY
WRRDY
STDRDY
SYNC
The following specifications apply to the ADC12041, 13-bit data bus width, V
= 50 pF on data I/O lines
Digital Timing Characteristics
Notes on Specifications
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-
tions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
tion to ambient thermal resistance), and T
in the V package, when board mounted, is 55˚C/W, and in the SSOP package, when board mounted, is 130˚C/W.
Note 5: Human body model, 100 pF discharged through 1.5
Note 6: Each input is protected by a nominal 6.5V breakdown voltage zener diode to GND, as shown below, input voltage magnitude up to 5V above V
conversions.
Note 7: V
comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-
tween −1 to 0 and 0 to + 1 (see Figure 8 ).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting out-
put value when the inputs are driven with a 2.5V input.
Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V
the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
below GND will not damage the ADC12041. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion
can occur if these diodes are forward biased by more than 50 mV. As an example, if V
Symbol
A
+ and V
REFCM
(Reference Voltage Common Mode Range) is defined as
D
Rising Edge of RD
to Rising Edge of RDY
Active Edge of WR
to Rising Edge of RDY
Active Edge of WR
to Falling Edge of RDY
Minimum SYNC Pulse Width
+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
A
= 25˚C and represent most likely parametric norm.
Parameter
IN
) at any pin exceeds the power supply rails (V
REF
(V
A
REF
(ambient temperature). The maximum allowable power dissipation at any temperature is P
+ − V
CLK
REF
−) given as + 4.096V, the 12-bit LSB is 1.000 mV.
= 12 MHz.
k resistor.
(Continued)
WMODE = “1”
WMODE = “0”. Writing the
RESET Command into the
Configuration Register
7
IN
Conditions
<
A
+ is 4.50 V
GND or V
Jmax
= 150˚C, and the typical thermal resistance (
IN
A
DC
+ = V
>
, full-scale input voltage must be 4.55 V
(V
Jmax
A
+ or V
D
+ = 5V, f
, (maximum junction temperature),
D
+)), the current at that pin should be limited to 30
DS012441-4
(Note 10)
Typical
CLK
1.4
24
37
5
A
+ and V
= 12 MHz, t
D
+ at the specified extremes.
(Note 11)
Dmax
+
Limits
pin to assure conversion/
2.5
38
60
10
DC
f
= (T
JA
= 3 ns and C
) of the ADC12041
to ensure accurate
JA
Jmax
(package junc-
www.national.com
− T
ms (max)
ns (max)
ns (max)
ns (min)
A
A
(Limit)
+ or 5V
)/
Unit
JA
L
or