adv7802 Analog Devices, Inc., adv7802 Datasheet
adv7802
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adv7802 Summary of contents
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... ADV7802 capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7802 to simultaneously process CVBS and standard definition RGB signals. The ADV7802 contains two main processing sections. The first ...
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... ADV7802 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Electrical Characteristics ............................................................. 4 Video Specifications ..................................................................... 6 Timing Characteristics ................................................................ 7 Timing Diagrams .......................................................................... 8 Analog Specifications ................................................................... 9 Absolute Maximum Ratings .......................................................... 10 Package Thermal Performance ................................................. 10 Thermal Resistance .................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 REVISION HISTORY 8/11—Revision D: Initial Version Theory of Operation ...
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... Data Sheet MUX FUNCTIONAL BLOCK DIAGRAM FORMATTER AND FIFO OUTPUT MUX INPUT Figure 2. Rev Page ADV7802 06654-002 ...
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... ADV7802 SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 3. 3.45 V, DVDD = 1. 1.85 V, DVDDIO = 3 3.6 V, DVDDIO_SDRAM = 2. 2.65 V (DDR), DVDDIO_SDRAM = 3 3.4 V (SDR), PVDD = 1. 1.89 V, nominal input range 1 otherwise noted. Table 1. Parameter 1 STATIC PERFORMANCE 2, 3 Resolution (Each ADC) Integral Nonlinearity 4 Differential Nonlinearity 4 POWER REQUIREMENTS 5 Digital Core Power Supply ...
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... Maximum INL and DNL specifications obtained with part configured for component video input. 5 Guaranteed by characterization. V and V levels obtained using default drive strength Symbol Test Conditions 0 SOURCE 3 SINK I LEAK C OUT Rev Page ADV7802 Min Typ Max Unit 2 μ ...
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... ADV7802 VIDEO SPECIFICATIONS AVDD = 3. 3.45 V, DVDD = 1. 1.85 V, DVDDIO = 3 3.6 V, DVDDIO_SDRAM = 2 2.6 V (DDR), DVDDIO_SDRAM = 3 3.4 V (SDR), PVDD = 1. 1. Table 2. Parameter 1 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS (SDP) Horizontal Lock Range ...
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... Negative clock edge to start of 13 valid data t End of valid data to negative 14 clock edge t HS_IN1, VS_IN1, HS_IN2, VS_IN2 17 DE_IN, data inputs t HS_IN1, VS_IN1, HS_IN2, VS_IN2 18 DE_IN, data inputs Rev Page ADV7802 Min Typ Max Unit 28.63636 MHz ±50 ppm 14.8 90 kHz 12.825 150 MHz 400 kHz 0 ...
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... ADV7802 TIMING DIAGRAMS SDA1/SDA2 SCLK1/SCLK2 P0 TO P53, VS_OUT, HS_OUT, FLD_DE_OUT P0 TO P53, VS_OUT, HS_OUT, FLD_DE_OUT CLKIN HS_IN1, VS_IN1, CONTROL HS_IN2, INPUTS VS_IN2, DE_IN P30 TO P39, P40 TO P43, P44 TO P53 Figure Timing LLC ...
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... SCART RGB input ( signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y signal) Component input (Pr, Pb signals) PC RGB input ( signals) SDP only SDP only SDP only SDP only Rev Page ADV7802 Min Typ Max 10 20 2.0 CML + 0.8 CML − 0.8 1.6 CML − 0.292 CML − ...
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... ADV7802 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD to AGND 4.0 V DVDD to DGND 2.2 V PVDD to AGND 2.2 V DVDDIO to DGND 4.0 V DVDDIO_SDRAM to 2.7 V DGND_SDRAM (DDR) DVDDIO_SDRAM to 4.0 V DGND_SDRAM (SDR) DVDDIO to AVDD −0 +0.3 V DVDDIO to DVDD −0 DVDDIO_SDRAM to DVDD (DDR) −0 +2.5 V DVDDIO_SDRAM to DVDD (SDR) −0 +3.3 V AVDD to PVDD − ...
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... DVDDIO_SDRAM 37 DGND_SDRAM 38 SDRAM_A10 39 SDRAM_BA1 40 SDRAM_BA0 41 SDRAM_CS 42 SDRAM_RAS 43 SDRAM_CAS 44 ADV7802 TOP VIEW (Not to Scale) Figure 7. Pin Configuration Rev Page ADV7802 132 P48 P49 131 P50 130 P51 129 P52 128 127 P53 126 DE_IN 125 VS_IN1 124 VS_IN2 INT 123 122 ...
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... ADV7802 Table 7. Pin Function Descriptions Pin No. Mnemonic 1 to 14, 155 to 158, 161 P29 169, 172 to 174 15, 79, 143, 170 DVDDIO 16, 22, 35, 59, 77, 82, 138, DGND 144, 160, 171, 176 17 LLC 18 CS/HS_OUT 19 SFL/SYNC_OUT 20 FLD_DE_OUT 21 VS_OUT 23, 36, 60, 76, 137, 159, 175 DVDD 24 to 34, 39 ...
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... HS_IN2 is used as the I I ALSB selects the address for the ADV7802 control. ALSB set to Logic 0 configures the address for a write to the input/output port of 0x40. ALSB set to Logic 1 configures the address for a write to the input/output port of 0x42. ...
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... VCR. ADLLT enables the ADV7802 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs, VCR players, and camcorders). Frame TBC ensures stable clock synchronization between the decoder and the downstream devices ...
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... Differential phase (DP), typically 0.45° VBI DATA PROCESSOR The VBI data processor (VDP) of the ADV7802 is capable of slicing multiple vertical blanking interval data standards on SD video and component video. The VDP decodes the VBI data on the incoming CVBS/YC or YUV data processed by the SDP core. ...
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... Integrated programmable antialiasing filters • 176-lead × 26 mm, RoHS-compliant LQFP For more detailed product information about the ADV7802, contact a local Analog Devices sales representative. SINGLE DATA RATE (SDR) The ADV7802 uses SDR external memory synchronizer operation, or 3D-DNR nonconcurrent operation. ...
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... The external loop filter components for the ELPF pins should be placed as close as possible to the respective pins. Figure 8 shows the recommended component values. PIN 86 (ELPF1) PIN 88 (ELPF2) 1.69kΩ 160Ω 10nF 39nF 82nF 820nF PVDD = 1.8V PVDD = 1.8V Figure 8. ELPF Components Rev Page ADV7802 ...
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... ADV7802 TYPICAL CONNECTION DIAGRAMS Figure 9. Typical Connection Diagram (External DDR Memory) Rev Page Data Sheet ADV7802 ...
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... Data Sheet ADV7802 Figure 10. Typical Connection Diagram (External SDR Memory) Rev Page ADV7802 ...
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... ADV7802 Figure 11. Typical Connection Diagram (No External Memory) Rev Page Data Sheet U2 ADV7802 ...
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... These modes are under the I OP_FORMAT_SEL[5:0]. PIXEL DATA OUTPUT MODES HIGHLIGHTS The ADV7802 has a flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. See Table 8 and Table 9 for more information on each mode. The output pixel port features include • ...
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... ADV7802 Table 8. SDR Pixel Port Output Modes OP_FORMAT_SEL [5:0] 0x00 0x01 8-Bit SDR 10-Bit SDR ITU-656 ITU-656 Pixel Output Mode 1 Mode 1 P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 ...
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... Y1, Cb1, Cr1 Z Z Y0, Cb0, Cr0 Rev Page ADV7802 0x05 0x06 0x07 16-Bit SDR 20-Bit SDR 24-Bit SDR ITU-656 4:2:2 ITU-656 4:2:2 ITU-656 4:2:2 Mode 1 Mode 1 Mode ...
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... ADV7802 OP_FORMAT_SEL [5:0] 0x08 24-Bit SDR 24-Bit SDR ITU-656 4:2:2 ITU-656 4:2:2 Pixel Output Mode 2 Mode 3 P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 Y11 Y11 P28 ...
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... Rev Page ADV7802 0x2E 0x0B 0x0C 30-Bit 24-Bit SDR 36-Bit SDR 36-Bit SDR SDR 4:4:4 4:4:4 4:4:4 4:4:4 Mode 1 Mode 1 Mode 1 Mode R11 R11 G2 R8 R10 R10 ...
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... ADV7802 OP_FORMAT_SEL [5:0] 0x28 16-Bit and 8-Bit SDR 4:2:2 Mode 1 Pixel Output Parallel Output P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 Main Y7 P28 Main Y6 P27 ...
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... Dual Parallel Output Pin Mode 0 48-Bit Dual Pin Mode 1 Aux Y11, Cb11, Cr11 R7-0 R7-0 Aux Y10, Cb10, Cr10 R6-0 R6-0 Aux Y9, Cb9, Cr9 R5-0 R5-0 Aux Y8, Cb8, Cr8 R4-0 R4-0 Aux Y7, Cb7, Cr7 R3-0 R3-0 Aux Y6, Cb6, Cr6 R2-0 R2-0 Aux Y5, Cb5, Cr5 R1-0 R1-0 Aux Y4, Cb4, Cr4 R0-0 R0 ADV7802 0x0F ...
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... ADV7802 Table 9. DDR Pixel Port Output Modes OP_FORMAT_SEL [5:0] 0x10 8-Bit DDR ITU-656 Pixel Output Clock Rise Clock Fall P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 ...
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... Rev Page ADV7802 0x13 0x14 12-Bit DDR YCrCb 12-Bit DDR YCrCb 4:2:2 Mode 2 4:2:2 Mode 3 Clock Rise Clock Fall Clock Rise Clock Fall ...
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... ADV7802 OP_FORMAT_SEL [5:0] 0x15 12-Bit DDR RGB 4:4:4 Pixel Output Clock Rise Clock Fall P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 B7 R3 P28 B6 R2 P27 ...
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... Aux Cb3, Cr3 Aux Cb0, Cr0 Aux Y0 Aux Cb2, Cr2 Z Z Aux Cb1, Cr1 Z Z Aux Cb0, Cr0 Rev Page ADV7802 0x39 0x3A 24-Bit and 12-Bit DDR 4:2:2 Mode 1 Parallel Output (CLK/2) Clock Fall Clock Rise Clock Fall Main Y1 Main Y1 Main Y0 ...
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... ADV7802 OP_FORMAT_SEL [5:0] 0x3B 24-Bit and 12-Bit DDR 4:2:2 Mode 2 Parallel Output (CLK/2) Pixel Output Clock Rise P53 Main Y3 P52 Main Y2 P51 Main Y1 P50 Main Y0 P49 Z P48 Z P47 Z P46 Z P45 Main Cb3 P44 Main Cb2 P43 Main Cb1 P42 Main Cb0 P41 Z P40 ...
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... Y6, Cb6, Cr6 Y4, Cb4, Cr4 Y5,Cb5, Cr5 Y3, Cb3, Cr3 Y4, Cb4, Cr4 Y2, Cb2, Cr2 Y3, Cb3, Cr3 Y1, Cb1, Cr1 Y2, Cb2, Cr2 Y0, Cb0, Cr0 Y1, Cb1, Cr1 Z Y0, Cb0, Cr0 ADV7802 0x07 ...
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... SEATING 0.08 MAX 0.05 PLANE COPLANARITY VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADV7802BSTZ-80 0°C to +85°C ADV7802BSTZ-150 0°C to +85°C EVAL-ADV7802EB1Z RoHS Compliant Part. 0.75 1.60 0.60 MAX 0.45 176 1 PIN VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BG A Figure 12. 176-Lead Low Profile Quad Flat Package [LQFP] ...
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... Data Sheet NOTES Rev Page ADV7802 ...
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... ADV7802 NOTES I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 2 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06654-0-8/11(D) Rev Page Data Sheet ...