adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 8

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DSP DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU), shown in
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes eight serial ports, four precision clock
generators (PCG), and an input data port (IDP). The IDP pro-
vides an additional input path to the ADSP-21371 core,
configurable as either eight channels of I
gle 20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-21371’s serial ports.
Serial Ports
The ADSP-21371 features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports are enabled via eight programmable pins and simul-
taneous receive or transmit pins that support up to 16 transmit
or 16 receive channels of audio data when all four SPORTs are
enabled, or four full duplex TDM streams of 128 channels per
frame.
The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I
• I
• Packed I
• Left-justified sample pair mode
mode
2
S mode
2
S mode
Figure
1.
2
S serial data, or a sin-
Rev. 0 | Page 8 of 48 | June 2007
2
S
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional P-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
right justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral (Compatible) Interface
The ADSP-21371 SHARC processor contains two serial periph-
eral interface ports (SPIs). The SPI is an industry-standard
synchronous serial link, enabling the ADSP-21371 SPI-compat-
ible port to communicate with other SPI compatible devices.
The SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup-
porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI-compatible devices, either acting as a master or slave
device. The ADSP-21371 SPI-compatible peripheral implemen-
tation also features programmable baud rate and clock phase
and polarities. The ADSP-21371 SPI-compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
2
S protocols (I
2
S is an industry-standard interface com-
2
S channels (using two stereo
2
S modes, data-
2
S chan-
2
S or