adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 5

• Manufacturer Part Number: adsp-21462
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 2
processors.
Table 2. Processor Benchmarks
1
The ADSP-2146x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram
tural features:
The block diagram of the processor
following architectural features:
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
Divide (y/×)
Inverse Square Root
Assumes two files in multichannel SIMD mode
• Two processing elements, each of which comprises an
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Two programmable interval timers with external event
• On-chip SRAM
• JTAG test access port
• FFT, FIR, IIR accelerators
• DMA controller
• Digital applications interface that includes four precision
• Digital peripheral interface that includes two timers, one
ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
counter capabilities
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter with four independent asyn-
chronous sample rate converters, an input data port (IDP)
with eight serial ports, DTCP cipher, eight serial interfaces,
a 20-bit parallel input port (PDAP), and a flexible signal
routing unit (DAI SRU).
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
shows performance benchmarks for the ADSP-2146x
1
on Page 1
1
illustrates the following architec-
on Page 1
also illustrates the
Speed
(at 450 MHz)
1.11 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
10.0 ns
Rev. PrC | Page 5 of 62 | January 2009
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
FAMILY CORE ARCHITECTURE
The ADSP-2146x is code compatible at the assembly level with
the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and
ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-2146x shares architectural fea-
tures with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and
ADSP-2116x SIMD SHARC processors, as detailed in the fol-
lowing sections.
SIMD Computational Engine
The ADSP-2146x contains two computational processing ele-
ments that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the processor’s enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-2146x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on page
1). With the its separate program and data