ml675050 Oki Semiconductor, ml675050 Datasheet
ml675050
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ml675050 Summary of contents
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... The ML675050 also includes a Modulo Calculation Accelerator for Encryption / Decryption, which enables RSA encryption/decryption much faster than software based solution under the same conditions. A Battery Backup RAM is also integrated for safely storing crypto-key data. Therefore ML675050 is an ideal MCU for IC card reader/writer based applications. ...
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... Random Generator RAM WDT 16KByte Stand-By Battery Controller Backup RAM 2KByte Power (VBAT) Clock/Reset Control Controller (SIM) 2ch VBATVDD IOVDD FEDL675050-02 ML675050 ROMCS_N RAMCS_N ML675050 IOCSn_N RD_ N WR_N BSn_N XA[23:0] SDRAM XD[15:0] Controller SDCS_N SDRAS/CAS_N SDCKE_N SDCKE EXEC (Modulo) DD[3:0] CPO/CPI QVGA B/W LP/FLM LCD ...
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... XD8 166 XD9 167 IOVDD 168 GND 169 PH3 170 XD10 171 INDEX MARK XD11 172 XD12 173 XD13 174 XD14 175 XD15 176 Top View FEDL675050-02 ML675050 88 PF3 87 PF2 PF1 86 85 PF0 84 BS1_N 83 BS0_N 82 PE7 81 GND 80 IOVDD 79 WR_N 78 PE3 77 PE2 ...
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... RESET AIN5 AIN1 PB2 PB0 _N AIN2 AVDD AGND NTRST TEST2 RTC RTC PB1 PB5 PH7 CLK_N CLK_P FEDL675050-02 ML675050 PD3 PD7 SDCKE PF5 XA7 SDCAS RD_N PF4 XA6 PD4 _N SDRAS PH6 PE6 XA8 XA9 _N GND IOVDD PD5 XA10 XA11 ...
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... Timer bit1 TIMER2 IO Timer bit2 SCL1(note) IO I2C1 Clock DD0 O LCD Data 0 DD1 O LCD Data 1 DD2 O LCD Data 2 DD3 O LCD Data 3 FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O EXINT2 I INT input 2 uSOUT O SIO Tx EXREQ0 I DMA req. 0 EXACK0 O DMA ack. 0 EXINT0 I INT input 0 EXINT3 ...
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... MOSI0 IO SPI0 MOSI DATAENB O LCD Data Enable FLM O LCD Frame Synchronous Pulse DF O LCD AC Conversion CPI I LCD Clock Output SIM_ O SIM0 Voltage VCCL01 Control 1 SIM_ I SIM0 CRDDET0 Card Detect FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O EXINT1 I INT input 1 uSIN I SIO Rx Description 6/62 ...
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... PENC O USB Host Power Control OVC I USBHost Over Voltage signnal SIM_CLK1 O SIM1 Clock SIM_RST1 O SIM1 Reset SIM_RST0 O SIM0 Reset FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O EXINT0 I INT input 0 EXINT1 I INT input 1 EXINT5 I INT input 5 EXREQ1 I DMA req. 0 EXACK1 I DMA ack. 0 Description ...
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... Slave Select SCK1 IO SPI1 Clock SSn1 IO SPI1 Slave Select SIM_ I SIM1 CRDDET1 Card Detect RI I UART0 RI PUCTL O USBdevice Pull-up Control EXINT6 I INT input 6 for USBdevice VBUS FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O EXINT4 I INT input 4 EXINT5 I INT input 5 EXINT4 I INT input 4 Description 8/62 ...
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... GND GND Secondary Function Description Symbol I/O MISO1 IO SPI1 MISO MOSI1 IO SPI1 MOSI DSR I UART0 DSR DTR O UART0 DTR SIM_ O SIM0 Power VCCCNT0 Control SIM_ O SIM1 Voltage VCCL11 Control1 FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O EXINT2 I INT input 2 EXINT3 I INT input 3 Description 9/62 ...
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... GPIO H bit3 171 A3 XD10 IO Ext. Data 10 172 B3 XD11 IO Ext. Data 11 173 A2 XD12 IO Ext. Data 12 174 C3 XD13 IO Ext. Data 13 175 B2 XD14 IO Ext. Data 14 176 A1 XD15 IO Ext. Data 15 Secondary Function Description Symbol I/O SIM_ O SIM1 Power VCCCNT1 Control FEDL675050-02 ML675050 Tertiary Function Description Symbol I/O Description 10/62 ...
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... Internal Pull-up ○ Internal Pull- Internal Pull- ○ - ○ - ○ ○ Internal Pull-up ○ ○ - ○ - ○ ○ ○ ○ ○ - ○ FEDL675050-02 ML675050 Buffer type 5V tolerant [mA ○ ○ 4 ○ ○ ...
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... FEDL675050-02 ML675050 Buffer type 5V tolerant [mA ...
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... FEDL675050-02 ML675050 Buffer type 5V tolerant [mA ○ ...
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... Internal Pull-down - Internal Pull-down - - - - - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - - - - - - - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - Internal Pull-down - FEDL675050-02 ML675050 Buffer type 5V tolerant [mA ...
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... Debugging pin. Normally connect to ground level. (5) Debugging pin. Normally drive at High level. (6) Debugging pin. Normally leave open. (7) Debugging pin. Normally drive at High level. (8) Debugging pin. Normally connect to ground level. (18) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Primary Negative Primary Negative Primary Positive ...
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... General Purpose I/O port F (85, 86, 87, 88, 129, 130) General Purpose I/O port G (49, 67, 68, 99, 105, 106, 112, 146) General Purpose I/O port H (19, 42, 97, 98, 104, 125, 147, 170) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Primary/ Positive Secondary Primary ...
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... BS1_N is for MSB, BS0_N is for LSB. (83, 84) SDRAM clock (Same as operating frequency, Max. 64MHz) (111) Raw address strobe for SDRAM (121) Column address strobe for SDRAM (122) Clock enable for SDRAM (123) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Primary Positive Primary Positive Negative Primary / ...
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... DREQ. (23 DMA request signal, used when DMA controller configured for DREQ type (85 DREQ signal clear request. The DMA device responds to this output by negating DREQ. (86) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Positive/ Tertiary Negative Positive/ Tertiary ...
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... SIO transmit signal (19) I2C Data. This pin operates as NMOS Open drain. Connect pull-up resistor. (SDA0:20, SDA1:10) I2C Clock. This pin operates as NMOS Open drain. Connect pull-up resistor. (SCL0:21, SCL1:35) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Secondary Positive Secondary Positive Secondary ...
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... SIM_RST1:98) SIM Power supply voltage control 0. (SIM_VCCL00:112, SIM_VCCL10:42) SIM Power supply voltage control 1. (SIM_VCCL01:67, SIM_VCCL11:147) SIM External power supply regulator control. (SIM_VCCCNT0:146, SIM_VCCCNT1:170) SIM Card detection (H=Detected / L=Empty). (SIM_CRDDET0:68, SIM_CRDDET1:125) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Positive Secondary Positive Secondary Secondary ...
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... LCD signal convert switch. Switch signal to convert LCD drive waveform into AC (60) LCD Pannel clock intput. (62) Analog input for analog to digital converter (AIN0:27, AIN1:28, AIN2:29, AIN3:30 AIN4:31, AIN5:32, AIN6:33, AIN7:34) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Secondary Positive Secondary Positive Secondary ...
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... Analog to digital converter power supply. (25) PLL power supply. (PLLVDD1:64, PLLVDD2:70) GND for core and I/O. (4, 16, 38, 55, 66, 81, 94, 110, 127, 142, 152, 161, 169) GND for Analog to digiatal converter. (26) GND for PLL. (PLLGND1:65, PLLGND2:71) FEDL675050-02 ML675050 Primary/ Secondary/ Logic Tertiary Primary Positive Primary Positive 22/62 ...
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... Supports 16-bit devices Supports CBR auto-refresh and self-refresh Operates at the same clock MHz CPU Interrupt controller - LSI internal interrupt : 38 sources - LSI external interrupt: 7 sources (with 1 source being FIQ) - Seven levels of interrupt priorities can be set for each interrupt source. FEDL675050-02 ML675050 23/62 ...
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... Built-in 16-bit timer - Maximum overflow time is 8.3875 seconds (when operating at 32 MHz APB clock) - Watchdog timer mode provided - Interrupts or resets are generated according to settings. - Starting/stopping a watchdog timer - Clearing a watchdog occurrence factor - The watchdog timer cycle can be changed during watchdog timer operation. FEDL675050-02 ML675050 24/62 ...
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... Philips I2C bus specification Ver 2.1 compliant controller ´ 2ch - Supports multi-master mode. - Data transfer modes Standard mode (100 kHz) Fast mode (400 kHz) - 7-bit/10-bit address compatible - Clocks are stopped to synchronize data between master and slave. - Supports DMA transfer. FEDL675050-02 ML675050 25/62 ...
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... The master or slave mode can be selected. - Built-in 16-byte or 16-word (16-bit) FIFO on the transmitting side and receiving side - 8 bits (byte bits (word) can be selected as the transfer size. - Supports DMA transfer. - Built-in baud rate generator - 16 Mbps max. (APBCLK divided by 2) FEDL675050-02 ML675050 26/62 ...
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... JTAG boundary scan test executable Power management - Power saving mode · CPU halt mode: Stops only the CPU clock. · STOP mode: Stops all the clocks of the chip except RTC. · Standby mode: Turns power off, except for RTC and backup RAM FEDL675050-02 ML675050 27/62 ...
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... LFBGA package T STG Symbol Condition Min. V 1.35 DDCORE 2.7 V DDIO (*1) V 1.35 DDPLL V 1.35 BAT V 2.7 DDA f 0.032 cpu Ta 40 FEDL675050-02 ML675050 Rating Unit 0.3 to +2.0 0.3 to +4.6 0 +0.3 DDIO 0 +0.3 DDIO V 0.3 to +2.0 0.3 to +2.0 0.3 to +4.6 0 DDA +24 1203 mW 670 50 to +150 C (GND = 0 V) Typ ...
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... IH3 50k pull-down pins IL1 Normal pins IL2 5 V tolerant pins IL3 50k pull-up pins this voltage value. this voltage value. FEDL675050-02 ML675050 = 2 DDIO Typ. Max 0.3 DDIO 5.5 0.8 0.3 0.3 0.8 2.4 2.4 0.81 1.89 0.135 2.1 2.52 (*1) (*1) (*2) 0.45 (*2) 0 200 ...
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... V = 1.65 V, BAT V = 3.6 V DDIO DDOVBAT V = 1.65 V, _ST BAT V = 3.6 V DDIO =1.50V =3.3V, Ta=25 C DDPLL2 DDIO DDAD =1.65V =3.6V, Ta=85 C DDPLL2 DDIO DDAD FEDL675050-02 ML675050 Min. Typ. Max. Unit (*1) 50 (*1) (* (*1) (*2) 40 115 (*1) (*2) 0.1 1 (*1) (*2) 0.1 1 (*1) (*2) 0 (*1) 50 (*1) (*2) ...
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... Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from “0x3FE” to “0x3FF.” 1. DDCORE Min. Typ. 0.8 32 1.0 1 1.0 1.0 1.0 0 2.5 impedance – Aground) 1024. FEDL675050-02 ML675050 = 2 DDA Max. Unit 10.0 MHz 400 KHz 12 bit LSB 4.0 6.0 8.0 8.0 1.0 uA 31.25 uS 400 kHz – Aground) 1024. ...
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... When being driven steady state Average bit rate 11.97 (12 Mbps 0.25%) (V Condition Min 150 150 pF 75 1.3 Average bit rate 1.4775 (1.5 Mbps 0.25%) FEDL675050-02 ML675050 = 3 DDIO Target Max. Unit pins 2.5 V D+, D– 2.0 3.6 0 3 DDIO Typ. Max. Unit Target pins — ...
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... Symbol Condition Min 1.35 V — RV1 t 0 2.7 V — RV2 t — 1. FV1 t 2 — FV2 FEDL675050-02 ML675050 Typ. Max. Unit — 100 ms — 100 ms — 100 ms — 100 ms 33/62 ...
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... Core reset pulse width Reset pulse width Reset timing Symbol Condition Min. t — 10 CORERSTW t — 10 RSTW FEDL675050-02 ML675050 Typ. Max. Unit — — s — — s 34/62 ...
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... Symbol Condition f — RTC t — RTC t — RTCH t — RTCL FEDL675050-02 ML675050 Min. Typ. Max. Unit 8 — 16 MHz 62.5 — 125 ns 20 — — — — ns Min. Typ. Max. ...
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... Condition (* (* Symbol Condition F CPI F f CPI HC t CPI FEDL675050-02 ML675050 Min. Typ. Max. Unit — — 64 MHz 15.625 — — ns Min. Typ. Max. Unit — — 32 MHz 31.25 — — ns Min. Typ. ...
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... FEDL675050-02 ML675050 Typ. Max. Unit — 20 MHz — — — — — — — — ns — — — ...
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... – 6 — — HC FEDL675050-02 ML675050 Max. Unit Remarks The RD_N/WR_N ) pulse width and the read off time when ) accessing SRAM/ROM are the +3 parameters that can R2 R4 ...
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... FEDL675050-02 ML675050 ...
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... External ROM, external RAM write cycle (when a 32-bit write is performed during continuous write on a 16-bit bus) ROMCS_N/ RAMCS_N XA[23:0] BS0_N/ BS1_N WR_N XD[15:0] t CSWACC t t XAWACC XAWH BSWACC BSWH t WRW t t XDOS XDOH D1 FEDL675050-02 ML675050 t CSWH t t XAWACC XAWH BSWACC BSWH t WRW t t XDOS XDOH D2 42/62 ...
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... OKI Semiconductor ELECTRICAL CHARACTERISTICS (AC CHARACTERISTICS) (12) ROMAC register and timing parameters that can be set (Please see ML675050 User’s manual when refer to the ROMAC register in detail) The following timing parameters can be set: - Address setup - RD_N, WR_N pulse width - Data off timing (period for waiting the ROM output floating delay time from RD_N deassert) ...
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... SDC 0.5t – 3 — SDC 0.5t – 6 — 0.5t SDC 0.5t – 3 — SDC FEDL675050-02 ML675050 Unit Remarks The tRCD, tRAS, tRP and + 4 SDC tDPL when accessing SDRAM are the parameters + 3 SDC that can be set by the DRPC register SDC See Table below for details. ...
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... SDRAS_N t SDRCD SDCAS_N WR_N BS0_N, BS1_N, SDCKE XD[15: SDXAD SDXAD CA1 SDCS SDCS SDCS t SDRAS t SDRAS t t SDCASD SDCAS t SDWE t t SDDQMD SDDQM t t SDXDI SDXDIH D1-1 FEDL675050-02 ML675050 t t SDCS SDCS t SDRP t t SDRASD SDRASD t SDWE t SDDQM t t SDXDI SDXDIH D1-2 47/62 ...
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... FEDL675050-02 ML675050 ...
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... OKI Semiconductor ELECTRICAL CHARACTERISTICS (AC CHARACTERISTICS) (15) DRPC register setting and parameters (tRCD, tRAS, tRP, tDPL) (Please see ML675050 User’s manual when refer to the DPRC register in detail) DRAM SPEC: DRAM characteristics parameter setting SDRAM DRAM SPEC [3:0] 0000 0001 0010 0011 0100 0101 ...
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... 15 FEDL675050-02 ML675050 Unit Remarks + +1) *: The address setup, RD_N/WR_N pulse width, and data off time + 4 when IO0 and accessed are the parameters + 4 that can be set by the IOAC register. ...
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... BS0_N/ BS1_N RD_N XD[15:0] External IO0,1 write timing IOCSn_N XA[23:0] BS0_N/ BS1_N WR_N XD[15: IOCSRACC IOCSRH t t IOXARACC IOXARH1 t t IOBSRACC t IORDW t t IOXDIS IOXDIH t t IOCSWACC IOCSWH t t IOXAWACC IOXAWH t t IOBSWACC IOBSWH t IOWRW t t IOXDOH IOXDOS FEDL675050-02 ML675050 IOBSRH1 51/62 ...
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... IOBSWACC BS0_N/ BS1_N WR_N XD[15:0 t IOXARH1 A1 t IOBSRH1 t IORDW t t IODIS IODIH D1 t IOXAWH A1 t IOBSWH t IOWRW t t IOXDOH IOXDOS D1 FEDL675050-02 ML675050 t IOCSRH t t IOXARACC IOXARH2 IOBSRH2 IOBSRACC t IORDW t t IODIS IODIH D2 t IOCSWH t t IOXAWACC IOXAWH IOBSWH IOBSWACC t IOWRW ...
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... OKI Semiconductor ELECTRICAL CHARACTERISTICS (AC CHARACTERISTICS) (17) IOAC register and timing parameters that can be set (Please see ML675050 User’s manual when refer to the IOAC register in detail) The following timing parameters can be set: - Address setup - pulse width RD_N/WR_N - Data off timing (period for waiting the I/O output floating delay time from RD_N deassert) ...
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... Condition f SCL f LOW f HIGH t HD:STA CL=400pF t SU:STA t HD:DAT t SU:DAT t SU:STO 2 C bus device can be utilized in the standard I t SU:DAT HD:DAT HIGH SU:STA FEDL675050-02 ML675050 Min. Typ. Max. Unit 100 kHz 4.7 us 4.0 us 4.0 us 4.7 us 5.0 us 250 us 4.0 us Min. Typ. Max. Unit 400 kHz 1.3 us ...
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... CL=30pF sd (* 0.5 × t lead sck t 0.5 × t lag sck t 1 × t wssh sck FEDL675050-02 ML675050 Typ Max Unit 2046 × 1023 × (* 1.5 × sck 1.5 × sck 511 × sck ...
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... ( Note: For CPHA and CPOL, please see Section 24.4.1, “SPI Control Register.” of ML675050 User’s manual t lead sck sck w sck ...
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... The output delay increases at a rate of 0.4 ns/10 pF. * the cycle time of APB_CLK. PC Symbol Condition Min. (* × t sck PC (* × t wsck lead t 25 lag t dis FEDL675050-02 ML675050 Typ. Max. Unit 57/62 ...
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... SPI slave mode timing (CPHA = 1) SSN (input) t lead SCK (CPO L=0, input) SCK (CPO L=1, input) MISO (output (input) Note: For CPHA and CPOL, please see Section 24.4.1, “SPI Control Register.” of ML675050 User’s manual t sck t dd LSB LSB LSB t ...
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... Symbol Condition Min GPIOIH t 10 GPIOIL APB_CLK t 62.5 : GPIOOH A case of cpu continuou s access t 62.5 GPIOOL a register of GPIO in 32MHz FEDL675050-02 ML675050 Typ. Max. Unit ns ns Typ. Max. Unit 59/62 ...
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... FEDL675050-02 （ Unit ： mm ） Package material Epoxy resin Lead frame material Cu alloy Pin treatment Solder plating ( 5µm) Package weight (g) 1.86 TYP. Rev. No./Last Revised 1/Jan. 6, 2000 （ Unit ： mm ） ML675050 60/62 ...
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... OKI Semiconductor REVISION HISTORY Document Date No. FEDL675050-01 Nov. 10, 2006 FEDL675050-02 Mar. 1, 2007 Page Previous Current Edition Edition – – Final edition SIM interface descript correction FEDL675050-02 ML675050 Description 61/62 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL675050-02 Copyright 2006 Oki Electric Industry Co., Ltd. ML675050 62/62 ...