z85c30 ZiLOG Semiconductor, z85c30 Datasheet - Page 54
z85c30
Manufacturer Part Number
z85c30
Description
Cmos Scc Serial Communications Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z85C30.pdf
(71 pages)
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PS011705-0608
Table 6. Z85C30 Read/Write Timing (continued)
No Symbol
49b Trci
a. Parameter does not apply to Interrupt Acknowledge transactions.
b. Open-drain output, measured with open-drain test load.
c. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
d. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each device
separating them in the daisy chain.
e. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is
synchronized to PCLK falling edge, then TrC = 3TcPc.
f. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
f
Figure 33
Table 7
Figure 34
Table 8
Table 9
Figure 35
acknowledge timing, and reset timing, respectively.
Table 10
Parameter
RD or WR Fall to PC
Fall Setup Time
lists the Z85C30 general timing characteristics.
lists the Z85C30 system timing characteristics .
provides the Z85C30 Read/Write timing characteristics.
provides the Z80C30 Read/Write timing characteristics.
displays the Z85C30 general timing diagram.
displays the Z85C30 system timing.
through
Figure 37
display the Z80C30 Read/Write timing, interrupt
8.5 MHz
Min
0
CMOS SCC Serial Communications Controller
Max
10 MHz
Min
0
Product Specification
Max
Electrical Characteristics
16 MHz
Min
0
Max
50