z80180 ZiLOG Semiconductor, z80180 Datasheet - Page 69

• Manufacturer Part Number: z80180
• Description: Microprocessor Unit
• Manufacturer: ZiLOG Semiconductor

PS014004-1106
DMA Mode Register (DMODE)
Note:
When
made to the CPU.
To perform a software
WRITE
0 DMA and automatically sets
RESET
DWE1: DE1 Bit WRITE Enable (bit 5)—When performing any
software
always reads as
DWE0: DE0 Bit WRITE Enable (bit 4)—When performing any
software
always reads as
DIE1: DMA Interrupt Enable Channel 1 (bit 3)—When
termination channel 1 DMA transfer (indicated when
request to be generated. When
disabled.
DIE0: DMA Interrupt Enable Channel 0 (bit 2)—When
termination channel 0 of DMA transfer (indicated when
request to be generated. When
abled.
DME: DMA Main Enable (bit 0)—A DMA operation is only enabled when its
(
When
service routine. To restart DMA,
contents are already
to continue.
DMODE
DE0
for channel 0,
DE0 = 0
NMI
DIE0
.
access. Writing
DME
setting
is used to set the addressing and transfer mode for channel 0.
WRITE
WRITE
DIE0
occurs,
is cleared to
cannot be directly written. It is cleared to
and the DMA interrupt is enabled (
is cleared to
DE0
1
1
to
to
.
.
DME
DE1
DE0
and/or
DE1
1
). This
WRITE
DE0
,
,
0
for channel 1) and the
DWE1
DWE0
is reset to
during
DE1
0
to
WRITE
during
to
0
DIE0 = 0
DIE0 = 0
DME
to
must be written with
must be written with
disables channel 0 DMA. Writing
DE0
DE–
RESET
1
.
0
DME
automatically sets
, disabling DMA activity during the
RESET
(DMA Main Enable) to
,
and/or
DWE0
, the channel 0 DMA termination interrupt is
, the channel 0 DMA termination interrupt is dis-
.
is cleared to
.
must be written with
DE1
DME
must be written with a
DIE0 = 1
bit is set to
0
0
DE1 = 0
0
during the same access.
during the same access.
DME
during
DE0 = 0
0
), a DMA interrupt request is
by
to
1
) causes a CPU interrupt
DIE0
DIE0
.
NMI
RESET
1
DE0
) causes a CPU interrupt
, allowing DMA operations
1
.
0
DE0
is set to
is set to
during the same register
Microprocessor Unit
or indirectly set to
is cleared to
.
to
1
NMI
1
(even if the
enables channel
1
1
, the
, the
interrupt
DWE1
DWE0
Architecture
0
DE
during
Z80180
bit
1
by
63