lan9118 Standard Microsystems Corp., lan9118 Datasheet - Page 19

• Manufacturer Part Number: lan9118
• Description: Lan9118 High-performance Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
PIN
NO.
99, 98
20,28,
42,48,
55,61,
19,27,
34,41,
47,54,
81,85,
77,80,
60,96
86,88
100,
35,
10
97
89
9
2
NAME
Activity Indicator),
Internal Regulator
General Purpose
+3.3V I/O Power
Analog Ground
nLED1 (Speed
nLED2 (Link &
nLED3 (Full-
+3.3V Analog
I/O Ground
Indicator
Indicator),
I/O data,
Test Pin
Duplex
RBIAS
Power
Power
).
Table 2.5 System and Power Signals (continued)
SYMBOL
GPIO[2:0]/
LED[3:1]
GND_IO
VDD_IO
ATEST
VDD_A
RBIAS
VSS_A
VREG
DATASHEET
BUFFER
TYPE
IS/O12/
OD12
19
AI
P
P
P
P
P
I
NUM
PINS
1
1
3
1
8
8
3
4
DESCRIPTION
General Purpose I/O data: These
three general-purpose signals are
fully programmable as either push-
pull output, open-drain output or input
by writing the GPIO_CFG
configuration register in the CSR’s.
They are also multiplexed as GP LED
connections.
GPIO signals are Schmitt-triggered
inputs. When configured as LED
outputs these signals are open-drain.
nLED1 (Speed Indicator). This
signal is driven low when the
operating speed is 100Mbs, during
auto-negotiation and when the cable
is disconnected. This signal is driven
high only during 10Mbs operation.
nLED2 (Link & Activity Indicator).
This signal is driven low (LED on)
when the LAN9118 detects a valid
link. This signal is pulsed high (LED
off) for 80mS whenever transmit or
receive activity is detected. This
signal is then driven low again for a
minimum of 80mS, after which time it
will repeat the process if TX or RX
activity is detected. Effectively, LED2
is activated solid for a link. When
transmit or receive activity is sensed
LED2 will flash as an activity
indicator.
nLED3 (Full-Duplex Indicator). This
signal is driven low when the link is
operating in full-duplex mode.
PLL Bias: Connect to an external
12.0K ohm 1.0% resistor to ground.
Used for the PLL Bias circuit.
This pin must be connected to VDD
for normal operation.
3.3V input for internal voltage
regulator
+3.3V I/O logic power supply pins
Ground for I/O pins
+3.3V Analog power supply pins. See
Note 2.1
Ground for analog circuitry
Revision 1.5 (07-11-08)