lan9118 Standard Microsystems Corp., lan9118 Datasheet - Page 73

• Manufacturer Part Number: lan9118
• Description: Lan9118 High-performance Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
5.3.4
BITS
30:26
12-11
2-0
31
25
24
23
22
21
20
19
18
17
16
15
14
13
10
9
8
7
6
5
4
3
DESCRIPTION
Software Interrupt (SW_INT_EN)
Reserved
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN).
Reserved
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt (RXD_INT).
GP Timer (GPT_INT_EN)
PHY (PHY_INT_EN)
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
Reserved
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
INT_EN—Interrupt Enable Register
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of
the interrupt source regardless of whether the source is enabled as an interrupt in this register.
Offset:
5Ch
DATASHEET
73
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Revision 1.5 (07-11-08)
DEFAULT
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-