at89c51ac3-s3sim ATMEL Corporation, at89c51ac3-s3sim Datasheet - Page 18

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at89c51ac3-s3sim

Manufacturer Part Number
at89c51ac3-s3sim
Description
At89c51ac3 Enhanced 8-bit Microcontroller With 64kb Flash Memory
Manufacturer
ATMEL Corporation
Datasheet
Registers
18
AT89C51AC3
Table 2. CKCON0 Register
CKCON0 (S:8Fh)
Clock Control Register
Note:
Reset Value = x000 0000b
Number
Bit
7
-
7
6
5
4
3
2
1
0
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Mnemonic Description
WDX2
PCAX2
WDX2
T2X2
T1X2
T0X2
SIX2
Bit
X2
6
-
Reserved
The value read from this bits is indeterminate. Do not set this bit.
WatchDog clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (MODE 0 and 2)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer0 clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2"bits.
PCAX2
5
(1)
(1)
(1)
SIX2
(1)
4
T2X2
3
(1)
(1)
T1X2
2
4383D–8051–02/08
T0X2
1
X2
0

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