ds64ev400sqx National Semiconductor Corporation, ds64ev400sqx Datasheet - Page 6

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ds64ev400sqx

Manufacturer Part Number
ds64ev400sqx
Description
Programmable Quad Equalizer
Manufacturer
National Semiconductor Corporation
Datasheet
www.national.com
SIGNAL DETECT and ENABLE TIMING
t
t
t
t
ZISD
IZSD
OZED
ZOED
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at V
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (J
1; J
Symbol
IN
is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
TRI-STATE to input SD Delay
Input to Tri-Sate SD Delay
EN TRI-STATE to Output Delay
EN Output to TRI-STATE Delay
Parameter
P-P
sine wave) under typical conditions.
Propagation delay measurement
at V
mV
microstrip FR4
(Figure 1, 4)
(Note 7)
Propagation delay measurement
at EN input to V
P
FR4
(Figure 1, 4)
(Note 7)
, 100 Mbps, 40” of 6 mil microstrip
P-P
IN
DD
, 100 Mbps, 40” of 6 mil
to SD output, V
= 3.3V or 2.5V, T
OUT
2
Conditions
– J
IN
6
2
O
). J
, V
OUT
IN
A
IN
= 800 mV
is the random jitter at equalizer outputs in ps-rms, see point C of Figure
= 25°C., and at the Recommended Operation Conditions at the time of
= 800
P-
Min
Typ
400
150
35
5
Max
Units
ns
ns
ns
ns

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