max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 15

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

When a frame is ready to send from the MAX2986 to
the external host, the MAX2986 asserts MIIRXDV after
an IFG (which is about 0.96µs), while there is no trans-
mission session in progress (with respect to MIICRS). A
receive process cannot start while a transmission is in
progress.
While the MAX2986 keeps MIIRXDV high, it sends 1
byte of data on MIIDAT for each positive edge on
Figure 13. Buffering (FIFO) Interface Receive Process from the
External Host View
Figure 14. Receive Timing of the Buffering (FIFO) Interface
'0'
MIIRXDV
MIIDAT
BUFRD
READ LENGTH
Integrated Powerline Digital Transceiver
______________________________________________________________________________________
MIIRXDV
START
(MSB)
'1'
FIFO Signal Timing—Receiving
FRAME LENGTH
NO
(MSB)
FIFO INTERFACE
FRAME LENGTH
READ LENGTH
READ FROM
COUNTER =
(LSB)
FRAME LENGTH
YES
(LSB)
DATA
BUFRD. The first 2 bytes represent frame length in
MSB-first format. After the last byte of data is received,
the MAX2986 resets MIIRXDV. The direction of bidirec-
tional data pins is controlled through BUFCS and
BUFRD pins. The MAX2986 enables data output drivers
when BUFCS = 0 and BUFRD = 0. The interactions
between the external host and the MAX2986 baseband
is shown in Figure 13 and the overall receive timing of
the buffering interface is illustrated in Figure 14, with
details in Figure 15 and Table 8.
Figure 15. FIFO Interface—Detailed Receive Timing
Table 8. FIFO Interface—Receive Timing*
* Per IEEE 802.3u standard.
** The default value of the debounce parameter is 3.
PARAMETER
DATA
t
t
OH
MIIRXDV
OV
MIICRS
MIIDAT
BUFRD
DATA
Valid after negative
edge of BUFRD
Hold after positive
edge of BUFRD
DESCRIPTION
DATA
t
OV
t
Debounce**
OH
MIICLK
MIN
+ 3
0
UNITS
ns
ns
15