max2986cxv Maxim Integrated Products, Inc., max2986cxv Datasheet - Page 9

• Manufacturer Part Number: max2986cxv
• Description: Integrated Powerline Digital Transceiver Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

Figure 3 illustrates the connections between MAC and
PHY in MII mode. Although the Tx and Rx data paths
are full duplex, the MII interface is operated in half-
duplex mode. MIIRXDV is never asserted at the same
time as MIITXEN.
On transmit, the MAX2986 asserts MIICRS some time
after MIITXEN is asserted, and drops MIICRS after
MIITXEN is deasserted and when the MAX2986 is
ready to receive another packet. When MIICRS falls,
the Ethernet MAC times out an interframe gap (IFG)
(0.96µs typ) and asserts MIITXEN again if there is
another packet to send. This differs from the nominal
behavior of MIICRS in that MIICRS can extend past the
end of the packet by an arbitrary amount of time, while
the MAX2986 is gaining access to the channel and
transmitting the packet.
MACs in 10Mbps mode do not use a jabber timeout, so
there is no timing restriction on how long MIICRS can
assert (other than timeouts the MAX2986 may implement).
Transmissions are modulated onto the wire as soon as
the transfer begins, as the MII fills the MAX2986 buffer
faster than data needs to be made available to the
modulator. When a packet arrives at the MAX2986, it
attempts to gain access to the channel. This may not
happen before the entire packet is transferred across
the MII interface, so the MAX2986 buffers at least one
Ethernet packet to perform this rate adaptation.
Figure 3. MAC and PHY Connection in MII Mode
Integrated Powerline Digital Transceiver
_______________________________________________________________________________________
MII MAC and PHY Connections
802.3 MAC
ETHERNET
(MII)
CLOCK SOURCE (2.5MHz OR 25MHz)
RXCLK
TXCLK
TXEN
RXDV
CRS
TXD[3:0]
RXD[3:0]
RXER
MDC
MDIO
COL
GND
MIIDAT[3:0]
MIIDAT[7:4]
V
MIIRXDV
MIIMDIO
CC
MIITXEN
MIIRXER
MIIMDC
MIICLK
MIICRS
BUFWR
BUFRD
BUFCS
On receive, when the MAX2986 anticipates that it will
have a packet demodulated, it raises MIICRS to seize
the half-duplex MII channel, waits a short time (an IFG),
then possibly defers to MIITXEN (which may just have
been asserted) plus an IFG, and then raises MIIRXDV
to transfer the packet. At the end of the transfer, it
drops MIICRS unless the transmit buffer is full or there
is another receive packet ready to transfer. This is illus-
trated in Figure 4, where one receive transfer is fol-
lowed by a second, which defers to MIITXEN. Data
reception needs to have priority over transmission to
ensure that the buffer empties faster than packets
arrive off the wire. The longest the receiver needs to
wait is the time to transfer one Tx frame plus an IFG or
approximately 134µs. However, minimum size frames
can arrive at a peak rate of one every 65µs, so the
receive-side buffer must accommodate multiple frames
(but only a little more than one Ethernet packet of data).
Figure 4. Receive Defer in MII Mode
INCOMING
MIIRXDV
RECEIVE
MIITXEN
MIICRS
INTERFACE
MII
MAX2986
IFG
MAC
PHY
DEFER
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