at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 180

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Logical Block Address
End of Data Transfer
End of Transfer Closing
Security Unit
180
AT85C51SND3B
•
In order to automatically and properly fill the spare zone, the logical block address must
be provided to the NFC. This is done by writing a 2-bytes descriptor byte by byte to the
NFLOG register according to Table 198. The first byte written is byte 0. The logical block
addresses must be updated each time the data flow reaches the beginning of new logi-
cal blocks.
Table 198. Logical Block Address descriptor Content
Reset Value = 0000 0000b for each byte.
In order to keep SMC compatibility, LBA will be organized as follow:
Header 00010b and parity “P” are handled by software. “A” represents the logical block
address.
When the data transfer stops, an interrupt is sent by the DFC macro to the CPU. The
CPU has then to stop the NFC macro by sending a STOP action. This action can also
be considered as an abort signal in a streaming mode. A STOP action makes the NFC
return cleanly to the idle state (NFRUN cleared): it does not stop a spare area
processing.
When the NFC stops following a STOP action, in the case of a write session, the user
must properly stop the page programming by copying old sectors to the new page.
Moreover, the spare zone shall also be managed by the software.
To do this, the user needs to know where the NFC stopped: the NFBPH and NFBPL
registers contain the byte position of the next data to be read or written. For example, it
contains 0 after a reset, and 528 if the controller stops in a 512B page after the spare
zone processing.
This register is incremented each time a byte is read through NFDATF or written
through NFDAT or NFDATF, spare zone included.
A read of NFDAT or NFADC does not increment the NFBP counter.
The NFBP counter can be updated by software. Anyway, this shall be done in debug
mode, and only when the NFC is not running.
Moreover, the NECC counter is updated when the controller reaches the end of the
page. It gives the number of ECC that is ready to be written/updated. This feature shall
be used when the flow does not start from the beginning of a page. For example, it con-
tains 3 if the flow starts at offset 512 till the end of the page. In this situation, the three
last ECC can be written/checked.
The Security Unit provides hardware mechanisms to protect NF content from any firm-
ware crash and prevent data loss and provides data recovery capability through ECC
management.
Offset
Byte
0 0 0 1
A A A A
read the ECC FIFO, (keeping the ECCs in memory), re-initialize it, resume the data
transfer, and to write all the ECC bytes at the end of the page.
0
1
Mnemonic
LBAH
LBAL
Byte
0 A A A
A A A P
Description
Logical Block Address (MSB).
Logical Block Address (LSB).
7632D–MP3–01/07