cat93hc46 Catalyst Semiconductor, cat93hc46 Datasheet - Page 6

• Manufacturer Part Number: cat93hc46
• Description: 1-kb High Speed Microwire Serial Eeprom
• Manufacturer: Catalyst Semiconductor

The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once write is enabled, it will
remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can
be used to disable all CAT93HC46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
falling edge of CS will start the self-timed clear cycle of
all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self-timed mode. (Note 1.) The ready/busy status of the
CAT93HC46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory locations will return to a logical “1” state.
Doc. No. 1008, Rev. H
DO
CS
SK
DI
DO
CS
SK
DI
1
1
1
0
1
1
A N
A N
A N-1
A N-1
HIGH-Z
CSMIN
HIGH-Z
. The
A 0
6
A 0
D N
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self-timed mode. The ready/busy status
of the CAT93HC46 can be determined by selecting the
device and polling the DO pin. It is not necessary for all
memory locations to be cleared before the WRAL
command is executed. Once written, the contents of all
memory locations will return to a logical “0” state.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
CSMIN
. The falling edge of CS will start the self-timed
t SV
D 0
t EW
t SV
t CS MIN
STATUS VERIFY
t EW
t CS MIN
STATUS
VERIFY
BUSY
BUSY
READY
READY
HIGH-Z
STANDBY
t HZ
STANDBY
t HZ
HIGH-Z