psf21911 ETC-unknow, psf21911 Datasheet
psf21911
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psf21911 Summary of contents
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ICs for Communications ISDN Echocancellation Circuit for Terminal Applications IEC-Q TE PSB 21911 Version 5.2 PSF 21911 Version 5.2 Data Sheet 11. ...
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PSB 21911 Revision History: Previous Releases: Page Subjects (changes since last revision) For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http://www.siemens.de/Semiconductor/address/address.htm. Edition ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Applications with ELIC on the Linecard (PBX .90 2.8 Reset . . . . . . . . . ...
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List of Figures Figure 1: Stand-Alone Mode (left) and µP Mode (right Figure 2: Logic Symbol µP ...
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Figure 43: Power Supply Blocking ...
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List of Tables Table 1: Microprocessor Bus Interface ...
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Overview The PSB 21911, IEC-Q TE Version 5. specific derivative of the PEB 2091, IEC-Q for terminal and small PBX applications. It features all necessary functions required for NTs and terminal applications like PC add-on cards and ...
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ISDN Echocancellation Circuit for Terminal Applications IEC-Q TE Version 5.2 1.1 Features • ISDN U-transceiver with IOM-2 and optional micro- processor interface • Compatible to NT modes and TE mode of PEB 2091 IEC-Q V5.1 • Perfectly suited for terminal ...
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Logic Symbol µP Mode Figure 2 Logic Symbol µP Mode Semiconductor Group Logic Symbol µP Mode 10 PSB 21911 PSF 21911 11.97 ...
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Logic Symbol Stand-Alone Mode Figure 3 Logic Symbol Stand-Alone Mode Semiconductor Group Logic Symbol Stand-Alone Mode 11 PSB 21911 PSF 21911 11.97 ...
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Pin Configuration N.C. N.C. TP FSC DCL CLS A3/MS0 N.C. DS/RD/MTO CDOUT/A2/MS1 CDIN/A1/MS2 MCLK/DISS D6/AD6/PCA1 D5/AD5/PCA0 N.C. N.C. Figure 4 Pin Configuration P-LCC-44 and T-QFP-64 Package (top view) Semiconductor Group ...
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Pin Definitions and Functions The following tables group the pins according to their functions. They include pin name, pin number, type and a brief description of the function. Pin No. Symbol Stand- P-LCC-44 T-QFP64 alone Power Supply Pins 1, ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone 24 43 GNDd 25 44 GNDd 33 55 MS0 35 58 MS1 Semiconductor Group Pin Definitions and Functions I/O Function µP mode I GNDd Must be connected to GNDd in stand- alone mode. ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone 36 59 MS2 28 47 RES Power Controller Interface Pins 44 5 PCD0 43 4 PCD1 Semiconductor Group Pin Definitions and Functions I/O Function µP mode I Mode Selection 2 refer to table ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone 42 3 PCD2 39 62 PCA0 38 61 PCA1 41 2 PCRD Semiconductor Group Pin Definitions and Functions I/O Function µP mode I/O Data Bus 2 of Power Controller Interface (PU) Internal pull-up. ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone 40 1 PCWR 19 36 INT 37 60 DISS 21 38 PS1 22 39 PS2 Semiconductor Group Pin Definitions and Functions I/O Function µP mode O Power Controller Bus Write Request Low active. ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone Miscellaneous Function Pins 10 22 XOUT 11 23 XIN 17 32 DOD TP1 Semiconductor Group Pin Definitions and Functions I/O Function µP mode XOUT O Crystal OUT To ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone 32 54 CLS 12 24 PMOD MTO 6, 9, 11, not 15, 20, 25, used 27, 31, 33, 34, 40, 48, 49, 50, 51, 63, 64 Semiconductor Group Pin Definitions ...
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Pin No. Symbol P-LCC-44 T-QFP64 Stand- alone ® IOM -2 Pins 31 53 DCL 30 52 FSC 26 45 DIN 27 46 DOUT U-Interface Pins 15 29 AIN 14 28 BIN 6 16 AOUT 4 13 BOUT PU: internal pull-up ...
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Microprocessor Bus Interface (Overview) The table below gives an overview of the different microprocessor bus modes. Table 1 Microprocessor Bus Interface Pin number Stand-alone mode P-LCC T-QFP PMODE = PCD0 43 4 ...
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System Integration Due to the IOM-2 interface the IEC-Q TE can be combined with a variety of other devices to fit in numerous applications. This chapter only shows some typical applications of the IEC-Q TE. 1.7.1 ISDN PC Adapter ...
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ISDN Stand-Alone Terminal with POTS Interface The IEC-Q TE can be integrated in a microcontroller based stand-alone terminal (figure 6) that is connected to the communications interface of a PC. The PSB 2132 SICOFI-TE enables connection of analog terminals ...
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ISDN Feature Phone An ISDN feature phone with U-interface can be built using the IEC-Q TE together with the ARCOFI-SP and the ICC. Figure 7 ISDN Feature Phone Semiconductor Group System Integration 24 PSB 21911 PSF 21911 11.97 ...
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ISDN-Modem PC Card The combination of the IEC-Q TE and a PSB 7115 ISAR 34 allows to build an ISDN- modem PC card . Figure 8 ISDN-Modem PC Card Semiconductor Group System Integration 25 PSB 21911 PSF 21911 11.97 ...
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Functional Description 2.1 Operating Modes The default configuration after power-on or external reset depends on the state of the PMODE pin. The cases µP mode and stand-alone mode have to be distinguished: µP mode (PMODE = VDD) In µP ...
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Table 3 Test Modes Test-Mode 1) Master-Reset 2) Send Single-Pulses 3) Data-Through Normal 1) Used for Quiet Mode and Return Loss measurements 2) Used for Pulse Mask measurements 3) Used for Insertion Loss, Power Spectral Density and Total Power measurements ...
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Device Architecture In µP mode the following interfaces and functional blocks are used: • IOM-2 interface • Microprocessor interface • U-transceiver • Clock Generation • Reset • Factory Test Unit Figure 9 IEC-Q TE Device Architecture (µP Mode) Semiconductor ...
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In stand-alone mode the following interfaces and functional blocks are used: • Mode Selection • IOM-2 interface • IOM-2 configuration • U-transceiver • Clock Generation • Reset • Power Controller Interface • Factory Test Unit Figure 10 IEC-Q TE Device ...
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IOM -2 Interface The IOM-2 interface is used to interconnect telecommunication ICs. It provides a symmetrical full-duplex communication link, containing user data, control/programming and status channels. The structure used follows the 2B + 1D-channel structure of ISDN. The ...
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mode is selected via pins MS0-2 in stand-alone mode and via bits MS0-2 in µP mode. Both the NT and TE mode utilize the same basic frame and clocking structure, but differ in the number and usage ...
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FSC R IOM Channel MON0 MON0 Figure 13 Definition of the IOM – C/I0 in IOM -2 Channel 0: ® two bits for the 16 kbit/s D-channel ...
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C/I2 in IOM -2 Channel 2: ® D-echo bits BAC-bit (Bus ACcessed). When the TIC bus is occupied the BAC-bit is low. S/G-bit (Stop/Go), available to a connected HDLC controller to determine ...
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IOM -2 Command / Indication Channels The Command/Indication channels carry real-time control and status information over the IOM-2 interface. C/I Channel 0 C/I channel 0 (C/I0) is available in both operational modes (NT and TE mode). The channel ...
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IOM -2 Monitor Channel The Monitor channel protocol is a handshake protocol used for programming and monitoring devices in Monitor channel "0" or "1". These can include the on-chip U- transceiver of the IEC well as ...
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Monitor Procedure ’Timeout’ The U-transceiver offers an automatic reset (Monitor procedure “Timeout”) for the Monitor routine. This reset function transfers the Monitor channel into the idle state (MR and MX set to high) by issuing “EOM” (End of Message) after ...
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Activation/Deactivation of IOM The IOM-2 clocks may be switched off if the U-transceiver is in state ’Deactivated’. This reduces power consumption to a minimum. In this deactivated state the clock lines are low and the data lines are high. ...
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SPU bit of the ISAC ICC to ’1’. Otherwise, the DU line has to be pulled to low via an I/O port of the microcontroller DCL is activated such that its first rising edge occurs with ...
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Microprocessor Interface The parallel/serial microprocessor interface can be selected to be either of the 1. Siemens/Intel non-multiplexed bus type with control signals CS, WR Motorola type with control signals CS, R/ Siemens/Intel multiplexed address/data bus ...
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U-Transceiver The U-interface establishes the direct link between the exchange and the terminal side over two copper wires. Transmission over the U-interface is performed at a rate of 80 kBaud. The code used is reducing two binary informations to ...
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Figure 16 U-Transceiver Block Diagram Semiconductor Group ITB10152 41 PSB 21911 PSF 21911 U-Transceiver 11.97 ...
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U-Frame Structure Each basic frame consists of 18 bits for the (inverted) synchronization word; 6 overheads bits are allocated for system functions, and 216 bits transfer the userdata channel (i.e. userdata of 12 IOM-frames is ...
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Table 6 U-Frame Structure Framing Quat 1 – 9 Positions Bit 1 – 18 Positions Super Basic Sync Frame # Frame # Word 1 1 ISW ...
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Cyclic Redundancy Check The cyclic redundancy check provides a possibility to verify the correct transmission of data. The checksum of a transmitted U-superframe is calculated from the bits in the D- channel, both B-channels, and the M4 bits according ...
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R IOM -2 NT ( G(u) CRC 1...CRC12 No =? (MON-1) NEBE NEBE (MON-8) Error Counter DU G(u) CRC 1 ... CRC FEBE (MON-8) Error Counter (MON-1) FEBE IEC-Q TE Figure 17 CRC-Process Semiconductor Group U ...
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Block Error Counters The U-transceiver provides internal counters for far-end and near-end block errors. This allows a comfortable surveillance of the transmission quality at the U-interface. In addition, MON-1 messages indicate the occurrence of near-end errors, far-end errors, and ...
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Testing Block Error Counters Figure 18 illustrates how the IEC-Q TE supports testing of the LT’s block error counters. Transmission errors are simulated with artificially corrupted CRCs. With two commands the cyclic redundancy checksum can be inverted in the downstream ...
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R IOM -2 EOC Transparent (MON-0) NCC (MON-0) ACK (MON-1) NEBE ERROR COUNT NEBE (MON-0) RTN (MON-0) ACK (MON-0) RCC (MON-0) ACK (MON-8) CCRC ERROR (MON-1) FEBE COUNT FEBE (MON-0) RTN (MON-0) ACK IEC-Q TE Figure 18 Block Error Counter ...
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Scrambler / Descrambler The scrambling algorithm as defined by ANSI T1.601 ensures that no sequences of permanent binary are transmitted. The algorithms used for scrambling and descrambling are described in figure 19. The scrambling/descrambling process is ...
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Embedded Operations Channel (EOC) EOC-data is inserted into the U-frame at the positions M1, M2 and M3 thereby permitting the transmission of two complete EOC-messages (2 12 bits) within one U-superframe. The EOC contains an address field, a data/message ...
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Table 7 EOC-Codes (cont’d) EOC Address d/m Information (hex d 2.5.2 EOC-Processor and MON-0 An EOC-processor on the chip is responsible for the correct insertion and extraction of EOC-data on the U-interface. The EOC-processor can ...
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MON-0 Structure 1. Byte MON-0 Addr: Address d/m: Data/Message i1-i8: EOC Code EOC Auto Mode Acknowledgment: All received EOC-frames are echoed back to the exchange immediately without triple-last-look address other than (000 a HOLD ...
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Table 8 Executed EOC Commands in Auto Mode EOC-code Direction (Hex LBBD 51 LB1 52 LB2 53 RCC 54 NCC FF RTN EOC Transparent Mode In transparent mode no acknowledgment, no triple-last-look and no ...
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Maintenance (MON-1) This category comprises commands and messages relating to maintenance bits of the U-interface and the self-test according to ANSI T1.601. The commands and messages may be mapped to the S/Q channel of the S/T-interface via the microprocessor. ...
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Table 9 Mon-1 S/Q-Channel Commands and Indications (cont’d) S/Q Direction SSSS (Bin NEBE FNBE NORM Normal. Return to normal (idle) state. This command Table 10 Mon-1 ...
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Overhead Bits (MON-2) MON-2-indications are used to transfer all overhead bits (M4, M5, M6) except those representing EOC- and CRC-bits. Starting with the ACT-bit, the order is identical to the position of the bits at the U-interface. Table 11 ...
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Control via Network – All Downstream bits. Automatic control via U-transceiver – ACT (Activation bit) – SAI (S Activity Indicator) can be controlled via MON-2 after MON-8 ’PACE’. – FEBE (Far-end Block Error) can additionally be controlled via MON-8-’SFB’. – ...
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In order to notify the controller of the initial system status, one MON-2-message is issued immediately after reaching the “Synchronized” state in NTmode. – The U-transceiver will not issue MON-2-messages while CRC-violations are detected. Because the CRC-checksum is transmitted ...
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Local Functions (MON-8) Local functions are controlled via MON-8-commands. The following tables give an overview of structure and features of commands belonging to this category. Format of MON-8-Messages 1. Byte MON-8 r: Register address – ...
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Table 13 Mon-8 Local Function Commands (cont’d) r Code Direction D7-D0 (Bin 1111 0000 0 1111 0100 0 1111 0010 0 1111 0001 0 1111 1111 0 1111 1011 Semiconductor Group Function U Local Commands CCRC Corrupt CRC. ...
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Table 13 Mon-8 Local Function Commands (cont’d) r Code Direction D7-D0 (Bin 1111 1010 ABEC 0 0000 0000 AID 0 ...
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State Machine Notation Rules The state machine includes all information necessary for the user to understand and predict the activation/deactivation status of the U-transceiver. The information contained in a state bubble is: State name, U-signal transmitted, Single Bits (Overhead ...
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Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN & DC), logical “OR” is written “or” and for a negation “/” is used. The start of a timer is indicated with “TxS” (“x” being equivalent to ...
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State Diagram SN0 T14 S Pending Timing Any State Pin-SSP or Pin-RES or DI SSP or RES SN0/SP Test DR ARL T12S SN 1 EC-Training AL DC LSEC or T12E SN 3 act = 0 ...
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Inputs to the U-Transceiver C/I-Commands AI Activation Indication The S-transceiver issues this indication to announce that the S-receiver is synchronized. The U-transceiver informs the LT side by setting the “ACT” bit to “1”. AR Activation Request INFO1 has been ...
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SSP Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. The pulses are issued at 1.5 ms intervals and have a duration of 12.5 s. The chip is in the “Test” state, the receiver ...
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DEA DEA-bit received from the LT-side – DEA = 0 informs the U-transceiver that a deactivation procedure has been started by the LT-side. – DEA = 1 reflects the case when DEA = 0 was detected by faults due to ...
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TL Wake-up signal received from the LT The U-transceiver is requested to start an activation procedure. The TL- criterion is fulfilled when 12 consecutive periods of the 10-kHz wake-up tone were detected. When in the “Pending Timing” state and automatic ...
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Outputs of the U-Transceiver Signals and indications are issued on IOM-2 (C/I-indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication The U-transceiver has established transparency of transmission in the direction IOM to U-interface NT1, ...
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INT Interrupt (Stand-alone mode only) A level change on input pin INT triggers the transmission of this C/I code in four successive IOM-2 frames. Please refer to page 96 for details. PU Power Up The U-transceiver provides IOM-2 clocks. Signals ...
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IOM-clocks are turned off. No signal is sent on the U-interface. The U-transceiver waits for a wake-up signal TL from the LT-side to start an activation procedure. To enter state ’IOM Awake’ a wake-up signal (DIN = 0) ...
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Pending Deactivation of S/T The U-transceiver has received the UOA-bit at zero after a complete activation of the S/ T-interface. The U-transceiver deactivates the S/T-interface by issuing DR in the C/I- channel. The value of the ACT-bit depends on its ...
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Synchronized 1 When reaching this state the U-transceiver informs the LT-side by sending the superframe indication (inverted synch.-word). The loop-back commands decoded by the EOC-processor control the output of the transmit signals: – Normal ACT and UOA = 0: – ...
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Wait for ACT Upon the receipt of AI, the ACT-bit is set to “1” and the NT waits for a response (ACT = 1) from the LT-side. The output of indications and transmit signals is as defined for the “Synchronized” ...
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Table 15 U-Transceiver C/I Codes Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AI Activation Indication AR Activation Request ARL Activation Request Local Loop DC Deactivation Confirmation DI Deactivation Indication DR ...
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Layer 1 Loop-Backs Test loop-backs are specified by the national PTTs in order to facilitate the location of defect systems. Four different loop-backs are defined. The position of each loop-back is illustrated in figure 23. IOM S-Bus Loop 2 ...
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Complete loop-back The complete loop-back comprises both B-channels and the D-channel. It may be closed either in the U-transceiver itself , in the S-transceiver external device. When receiving the EOC-command LBBD in EOC auto mode, the U-transceiver ...
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Analog Line Port The analog part of the IEC-Q TE consists of three main building blocks: – The analog-to-digital converter in the receive path – The digital-to-analog converter in the transmit path – The output buffer in the transmit ...
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Figure 24 DAC-Output for a Single Pulse Output Stage The output stage consists of two identical buffers, operated in a differential mode. This concept allows an output-voltage swing of 6.4 Vpp at the output pins of the IEC-Q TE. The ...
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Pulse Shape The pulse mask for a single positive pulse measured between AOUT and BOUT at a load given in the following figure. Figure 25 Pulse Mask for a Single Positive Pulse Hybrid The hybrid circuit for ...
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Access to IOM-2 Channels Important: This chapter applies only in µP mode In µP mode the microcontroller has access to the IOM-2 channels via the processor interface (PI) and registers Figure 26 Access to IOM-2 Channels (µP ...
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B-Channel Access Setting SWST:B1 (B2) to "1" enables the microprocessor to access B1 (B2)-channel data between IOM-2 and the U-transceiver. Eight registers (see table 16) handle the transfer of data from IOM-2 to the µP, from the µP to ...
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FIFOs are parallely shifted to DRU and DRI respectively. DRU and DRI have to be read before the next interrupt ISTA:D can occur, otherwise 8 bits will be lost. DWU and DWI have to be loaded with data ...
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C/I-commands to the U-transceiver have to be applied at least for two IOM-2 frames (250 µ considered as valid mode (i.e. 1.536 MHz DCL), the ADF2:TE1 bit is used to direct the C/I-channel access either to ...
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DIN DOUT P Interface SWST : MON = 0 MODE 1 : Monitor Channel access disabled DIN R IOM -2 Channel 0 DOUT P Interface SWST : MON = 1 ADF2 : MIN = 0 ADF2 : TE1 = 0 ...
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Monitor Channel Protocol The PI allows to program the IEC-Q TE Monitor channel in the way known from the PEB 2070 ICC. The Monitor channel operates on an asynchronous basis. While data transfers on the IOM-bus occur synchronized to ...
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Figure 30 Monitor Channel Protocol Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a "0" in MOSR:MAC, the Monitor Channel Active status ...
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When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), it sets the MR control bit MRC to "1" to enable the ...
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S/G Bit and BAC Bit in TE Mode Important: This chapter applies only in µP mode and if DCL = 1.536 MHz (TE mode). If DCL = 1.536 MHz the IOM-2 interface consists of three IOM-2 channels. The last ...
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Applications with ELIC on the Linecard (PBX) The S/G bit on DOUT (downstream) and the BAC bit on DIN (upstream) can be used to allow D-channel arbitration similar to the operation of the Upn interface realised with the OCTAT-P ...
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D-Channel Request by the Terminal Figure 31 illustrates the request for the HDLC-controller by the terminal. The start state is BAC = 1 at DIN after TD1 has expired. That causes the S/G bit to be set to the stop ...
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IOM -2 R ELIC xxxx C/I = HDLC occupied by other Terminal: C/I = 1100 HDLC assigned: C/I = 1000 HDLC ready: C/I = 1100 Figure 31 D-Channel Request by the Terminal Semiconductor Group U R IEC-Q k0 AFE/DFE Delay ...
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Reset Important: This chapter applies only in µP mode. Several resets are provided in the IEC-Q TE. Their effects are summarized in table 20. Table 20 Reset Reset Condition Power-on Power-on Hardware Pin RES = 0 Reset Watchdog Watchdog ...
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Power Controller Interface Important: This chapter applies only in stand-alone mode. A power controller interface is implemented in the PSB 21911 to provide comfortable access to peripheral circuits which are not connected directly to the microprocessor . Because this ...
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Communication with the power controller interface is established with local Monitor messages (MON-8) on IOM-2. The following two-byte messages are matched to the IEPC-power controller status register read and write operations but can be used in general, too. MON-8 1 ...
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Interrupt For every change at the input pin “INT”, the IEC-Q TE will transmit a C/I-channel code (0110 ), INT successive IOM-2-frames. The input condition of the “INT” pin is B sampled every 4 IOM-2-frames. An interrupt indication ...
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Operational Description 3.1 C/I Channel Programming Important: This chapter applies only in µP mode. P CIWU = C7 CICU ISTA = 02 Interrupt CIRU = 03 Figure 34 Example: C/I-Channel Use (all data values hexadecimal) Semiconductor Group C/I Channel ...
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Monitor Channel Programming Important: This chapter applies only in µP mode. The example on page 99 illustrates the read-out of the transceiver’s identification number (ID). It consists of the transmission of a two-byte message from the control unit to ...
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Example: Monitor Channel Transmission and Reception Basic Configuration, IOM-2 Clocks must be active w STCR = 0x15 w SWST = 0x06 w ADF2 = 0x48 Transmission r MOSR = 0x00 w MOX = 0x80 w MOCR = 0x30 r ISTA ...
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Layer 1 Activation/Deactivation Table 22 shows all U-interface signals as defined by ANSI. Table 22 U-Interface Signals Signal Synch. Word (SW SN0 no signal SN1 present SN2 present SN3 present SN3T present 1) TL SL0 no signal ...
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Complete Activation Initiated by LT Figure 35 depicts the procedure if the activation has been initiated by the exchange side. S/T IOM -2 INFO 0 DC INFO INFO 2 AR INFO 3 INFO 4 SBCX NT ...
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Complete Activation Initiated by TE Figure 36 depicts the procedure if the activation has been initiated by the terminal side. S/T IOM -2 INFO 0 DC INFO 0 INFO 1 TIM INFO 2 INFO 0 INFO ...
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Complete Deactivation S/T IOM -2 INFO 4 AI INFO INFO 0 INFO SBCX NT Figure 37 Complete Deactivation Semiconductor Group R U-Reference Point SL3T act = 1 dea = 1 uoa =1 SN3T ...
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Partial Activation (U Only) The IEC the “Synchronized 1” state (see state machine) after a successful partial activation. IOM-2-clocks DCL and FSC are issued. On DOUT the C/I-message “DC” as well as the LT-user data is sent. ...
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Activation Initiated by LT with U Active The S-interface is activated from the exchange with the command “AR”. Bit “UOA” changes to (1) requesting S-interface activation. R S/T IOM -2 INFO 0 DC INFO INFO 2 AR ...
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Activation Initiated by TE with U Active The TE initiates complete activation with INFO 1 leading to “SAI” = (1). Case 1 requires the exchange side to acknowledge the TE-activation by sending C/I = “AR”, Case 2 activates completely without ...
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S/T IOM -2 INFO 0 DC INFO 0 DI INFO INFO 2 INFO INFO 4 SBCX NT Figure 41 TE-Activation with U Active and no Exchange Control (case 2) Semiconductor Group R U-Reference Point ...
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Deactivating S/T-Interface Only Deactivation of the S-interface only is initiated from the exchange by setting the “UOA” bit = (0). S/T IOM -2 INFO 4 AI INFO INFO 0 INFO SBCX NT Figure 42 ...
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External Circuitry 3.4.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. Figure 43 Power Supply Blocking Semiconductor Group 109 PSB 21911 PSF 21911 External Circuitry 11.97 ...
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U-Interface The hybrid suggested for the PSB 21911 IEC identical to the hybrid recommended for the PEB 2091 IEC-Q. AOUT 681 BIN AIN 3. 6.8 nF BOUT Figure 44 U-Interface Hybrid Circuit Note: To ...
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Oscillator Circuit Figure 45 illustrates the recommended oscillator circuit. A crystal or an oszillator signal may be used 15.36 MHz 27 pF Figure 45 Crystal Oscillator or External Clock Source Crystal Parameters Frequency: Load capacitance: Frequency tolerance: ...
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Register Description Important: This chapter applies only in µP mode. The setting of the IEC µP mode and the transfer of data is programmed with registers. The address map and a register summary are given in table ...
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Table 24 Register Summary Add ress 0 D CICI CICU CICI CICU H 1 TEST1 TEST2 MS2 TE1 MTO DOD ...
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Interrupt Structure The cause of an intrerrupt is determinded by reading the Interrupt Status Register (ISTA). In this register, 7 interrupt sources can be directly read. Interrupt bits are cleared by reading the corresponding registers. ISTA:D is cleared after ...
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Monitor-Channel Interrupt Logic The Monitor Data Receive (MDR) and the Monitor End of Reception (MER) interrupt status bits have two enable bits, Monitor Receive Interrupt Enable (MRE) and MR-bit Control (MRC). The Monitor channel Data Acknowledged (MDA) and Monitor ...
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Registers ISTA-Register The Interrupt Status Register (ISTA) generates an interrupt for the selected channel. Interrupt bits are cleared by reading the corresponding register. Default CICI CICU D: D-channel Interrupt indicates an interrupt ...
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B2: B2-channel Interrupt indicates an interrupt every time B2-channel bytes arrive occurs after RB2I and RB2U have been read. MDA: Monitor Data Transmit Interrupt MDA = 1 indicates an interrupt after the MOSR:MDA or ...
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MDR: Monitor data receive mask MDR = 1 prevents an interrupt ISTA:MDR to actually influence the INT pin. MDR = 0 disables the function described above. B1: B1-channel mask prevents an interrupt ISTA:B1 to actually influence the ...
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STCR-Register The Status Control Register (STCR) selects the operating modes of the IEC given in table. Default MS2 Bit 7: reserved Set to ’0’ for future compatibility. Bit 6: reserved Set to ’0’ ...
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TM1: Test-Mode-Bit 1 This bit determines, in combination with STCR:TM2, the operation modes. See table below. TM2: Test-Mode-Bit 2 This bit determines, in combination with STCR:TM1, the operation modes. See table below. Test-Mode Normal Mode Send Single-Pulses Data-Through AUTO: Selection ...
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ADF2-Register Additional Features Register 2 (ADF2). Default TE1 MTO DOD TE1: Terminal Equipment Channel 1 TE1 = 1 enables the IEC write Monitor data on DOUT to the MON1 channel instead of the MON0 channel ...
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MOSR-Register The Monitor Status Register (MOSR) indicates the status of the Monitor channel. Default MDR MER MDA MDR: Monitor Channel Data Received Interrupt MDR = 1 generates an interrupt status after the receiving device has stored the ...
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MOCR-Register The Monitor Control Register (MOCR) allows to program and control the Monitor channel as described in the section 4.1.1. Default MRE MRC MXE MRE: Monitor Receive Interrupt Enable MRE = 1 enables the Monitor data receive ...
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CIRU-Register The Read C/I-code from U Register (CIRU) reads the C/I-code from the U-transceiver. Default C/I 7., 6. bits: Set to “0“. 5.-2. bits: Contain the C/I-indication coming from the U-transceiver. 1., 0. bits: Set ...
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CIRI-Register The Read C/I-code from IOM-2 Register (CIRI) reads the C/I-code from the IOM-2 interface. Default C/I C/I C/I 7., 6. bits: ADF2:TE1 = 1 indicates that the C/I-channel 1 in the TE mode can be accessed ...
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ADF-Register Additional Features Register (ADF). Default WTC2 WTC1 PCL1 WTC2, WTC1: Watchdog Controller The bit patterns “10“ and “01“ has to be written in WTC1 and WTC2 by the enabled watchdog timer within 132ms fails ...
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SWST-Register The Switch Status Register (SWST) selects the switching directions of the processor interface (PI). Default WT: Watchdog Timer enables the watchdog timer (page 39). WT= 0 disables the watchdog timer. ...
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BS: BS bit Operates in combination with SWST:SGL and ADF:CBAC bits to control the S/G bit and the BAC bit. For the functional description see Table 18 on page 89. SGL: Stop/Go Operates in combination with SWST:BS and ADF:CBAC bits ...
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B-Channel Access Registers Register Value after reset (hex) WB1U 00 RB1U 00 WB1I 00 RB1I 00 WB2U 00 RB2U 00 WB2I 00 RB2I 00 D-Channel Access Registers Register Value after reset (hex) DWU FF DRU FF DWI FF DRI FF ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Max. voltage applied at U-Interface V Max. voltage between GNDA1 (GNDA2) and GNDD Storage temperature Ambient temperature PSB 21911 PSF 21911 Thermal resistance (system-air) (system-case) Note: ...
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Line Overload Protection The maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse as outlined in the following figure. Figure 47 Test Condition for Maximum Input Current U-Transceiver Input ...
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Power Consumption All measurements with random data in active states. Mode Test Conditions Power up 5.00 V, open outputs 98 NT-Power down 5.00 V, open outputs 98 Temperature 5.00 V, open outputs 98 Temperature < 0 ...
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DC Characteristics VDD = 4.75 to 5.25 V Parameter H-level input voltage L-level input voltage L-level input leakage current for all pins except for PIN #11, #14, #15 H-level input leakage current for all pins except for PIN #11, ...
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U-transceiver Characteristics Receive Path Signal / (noise + total harmonic distortion) DC-level at AD-output Threshold of level detect Input impedance AIN/BIN Transmit Path Signal / (noise + total harmonic distortion) Output DC-level Offset between AOUT and BOUT 3) Signal amplitude ...
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Supply voltages VDD = + VDD 1 The maximum sinusoidal ripple on VDD Figure 49 Maximum Sinusoidal Ripple on Supply Voltage Semiconductor Group 0.25 V 0.25 V 1-2 is specified in the ...
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AC Characteristics ° Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V ...
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Figure 52 Siemens/Intel Write Cycle Figure 53 Siemens/Intel Multiplexed Address Timing Figure 54 Siemens/Intel Non-Multiplexed Address Timing Semiconductor Group Electrical Characteristics 137 PSB 21911 PSF 21911 11.97 ...
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Motorola Bus Mode Figure 55 Motorola Read Timing Figure 56 Motorola Write Cycle Figure 57 Motorola Non-Multiplexed Address Timing Semiconductor Group Electrical Characteristics 138 PSB 21911 PSF 21911 11.97 ...
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Microprocessor Interface Timing C = 50pF Load Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time DS delay after ...
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Serial Microprocessor Interface Timing The following 2 figures describe the read/write cycles and the corresponding address timing for the serial microprocessor interface: CS CCLK CDIN CDOUT Figure 58 Serial µP Interface Mode Write CS CCLK CDIN CDOUT Figure 59 ...
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Table 25 Timing Characteristics (serial µP interface mode 50pF Load Parameter Clock period Chip Select setup time Chip Select hold time CDIN setup time CDIN hold time CDOUT data out delay Semiconductor Group Electrical Characteristics Symbol min. t ...
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IOM -2 Interface Timing 5.4.3.1 NT Mode t r DCL FSC dDF DOUT t dDC DIN ® Figure 60 IOM -2 Timing in NT Mode Semiconductor Group T DCL wFH ...
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Table 26 IOM - Mode Parameter Signal Symbol Data clock rise/fall DCL 1) Clock period 1) Pulse width high/low 2) Clock period 2) Pulse width high/low 4) Frame width high FSC 5) Frame width high FSC Frame ...
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Power Controller Interface (Stand-Alone mode only) Figures 61 and 62 depict the timing for read and write operations. Figure 61 Dynamic Characteristics of Power Controller Write Access Figure 62 Dynamic Characteristics of Power Controller Read Access Semiconductor Group Electrical Characteristics ...
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Table 27 Power Controller Interface Dynamic Characteristics C = 25pF Load Parameter Write clock rise/fall Write with low Address set-up Data delay write Data delay read Set-up data read Read clock rise/fall Read width Semiconductor Group Signal Symbol min. t ...
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Reset Table 28 Reset Timing Parameter Symbol Power-on Reset t RST Active low state Watchdog Reset t RST Active low state Reset at pin RES t RST Active low state RST Figure 63 Reset Signal Semiconductor Group Limit Values Unit ...
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Package Outlines Plastic Package, P-LCC-44 (Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book ’Package Information’. SMD = Surface Mounted Device Semiconductor Group 147 PSB 21911 PSF 21911 Package ...
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Plastic Package, T-QFP-64 (Thin Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book ’Package Information’. SMD = Surface Mounted Device Semiconductor Group 148 PSB 21911 PSF 21911 Package Outlines Dimensions in ...
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External Component Sourcing The following tables contain transformers and crystals recommended by different manufacturers for use with Siemens ICs. No manufacturer can be recommended over another. Transformers marked with * shown positive test results. This list is not complete. ...
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Table 29 U-Transformer Information (cont’d) Part Number Comments Vacuumschmelze T60403 2kV -M6290-X054 -M6290-X058 2kV/4kV; Low bit error rate -M6276-X... 2kV; SMD TDK Valor Vogt 544 03 006 00 2kV, PTH Semiconductor Group External Component Sourcing Contacts (Phone) www.vacuumschmelze.de EU: +49 ...
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Table 30 Crystal Information Part Number Comments Frischer Electronic KVG NDK Saronix Tele Quarz Semiconductor Group External Component Sourcing Contacts (Phone) EU: +49 9131-33007 EU: +49 7263 648-0 J: (03)-460-2111 US: (408) 255-0831 US: (415) 856-6900 EU: +49 7268 8010 ...
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Glossary A/D Analog-to digital ADC Analog-to digital converter AGC Automatic gain control AIN Differential U-interface input ANSI American National Standardization Institute ARCOFI Audio ringing codec filter AOUT Differential U-interface output B 64-kbit/s voice and data transmission channel BCL Bit ...
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NCC Notify of corrupt CRC NEBE Near-end block error NT Network termination OSI Open systems interconnection PLL Phase locked loop PS Power supply status bit PSD Power spectral density PTT Post, telephone, and telegraph administration PU Power-up RCC Request corrupt ...
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Appendix A: Jitter on IOM-2 The output jitter on the IOM-2 clocks FSC and DCL/BCL may be higher than in versions 4.3 and older. The jitter on pin CLS is the same as in versions 4.3 and older. This does ...
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Appendix B:S/G Bit Control State Machine The state machine of the S/G bit control in TE mode is given in the following state diagrams. The values in the state diagrams are to be interpreted as follows: Figure 64 S/G Bit ...
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Figure 65 State machine (part 1) Semiconductor Group 1 PMODE = 0 Reset or ACT = 0 D0=0;SG (PMODE=ACT=TE=1) S and (BS=SGL=0) D0=0;SG=1 1 BS=1 and SGL=0 1 ...
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S/G go D0=0;SG=0 Figure 66 State machine (part 2) Semiconductor Group 8 HDLC ctrl D0=0;SG=1 BAC=0 TD1 set 9 BAC-Edge D0=0;SG=1 TD1 expired 10 Wait for EOC D0=0;SG=1 EOC=27 EOC=25 EOC=27 157 ...
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S/G go D0=1;SG=0 HDLC_Frame 20 HDLC-F go D0=0;SG=0 Figure 67 State machine (part 3) Semiconductor Group 14 HDLC ctrl D0=0;SG=1 BAC=0 TD1 set 15 BAC-Edge D0=1;SG=1 TD1 expired 17 Wait for EOC D0=1;SG=1 EOC=27 ...
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Table 31 State Machine Input Signals No. Signal name 1 PMODE ACT SGL 6 CBAC 7 EOC=25 8 EOC= set 10 T1 expired 11 TD1 set 12 TD1 expired 13 BAC Table ...
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Appendix C:Quick Reference Guide This chapter contains tables and figures often required when working with the PSB 21911. For additional technical information please refer to the relevant chapter. Semiconductor Group 160 PSB 21911 PSF 21911 Appendix 11.97 ...
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U-Transceiver State Diagram SN0 T14 S Pending Timing Any State Pin-SSP or Pin-RES or DI SSP or RES SN0/SP Test DR ARL T12S SN 1 EC-Training AL DC LSEC or T12E SN 3 Wait for SF ...
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Table 33 U-Transceiver C/I Codes Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AI Activation Indication AR Activation Request ARL Activation Request Local Loop DC Deactivation Confirmation DI Deactivation Indication DR ...
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A Absolute Maximum Ratings AC Characteristics 136 Activation/Deactivation Examples Analog Line Port 78 Auto Mode (EOC BAC Bit and S/G Bit 89 B-Channel Access 82 Block Error Counters 46 Blocking Capacitors 109 Channel 34 C/I ...
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Pin Configuration 12 Pin Definitions 13 Power Consumption 132 Power Controller Interface Power Supply 109 Pulse Shape 80 Q Quick Reference Guide R Register Address Map Register Summary 113 Reset 93 Reset Timing 146 S S/G Bit and BAC Bit ...