psf21911 ETC-unknow, psf21911 Datasheet - Page 93

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psf21911

Manufacturer Part Number
psf21911
Description
Isdn Echocancellation Circuit Terminal Applications Iec-q
Manufacturer
ETC-unknow
Datasheet
2.8
Important: This chapter applies only in µP mode.
Several resets are provided in the IEC-Q TE. Their effects are summarized in table 20.
Table 20
Reset
Power-on
Hardware
Reset
Watchdog
Software
Reset
The IOM-2 clocks DCL and FSC as well as MCLk are delivered during reset (except for
power-on).
The IEC-Q TE provides a low active reset output (pin RST) which is controlled by a
power-on reset and the watchdog timer. The watchdog is enabled by setting the
SWST:WT bit to “1”. Default after hardware reset of SWST:WT is "0". Please refer to
page 39 for information on how to use the watchdog timer.
Figure 32 illustrates the reset sources that have an impact on pin RST.
Figure 32 Reset Sources
Semiconductor Group
Reset
Reset
Condition
Power-on
Pin RES = 0
Watchdog
expired
C/I = 0001
Effect
Resets the state machine and all
registers
Resets the state machine and all
registers exept for STCR register
Resets no register and does not
affect the state machine
Resets the state machine and does
not affect the registers
Power-on
93
Pin RST active
yes
no
yes
no
PSB 21911
PSF 21911
Reset
11.97

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