adl5354 Analog Devices, Inc., adl5354 Datasheet
adl5354
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adl5354 Summary of contents
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... IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain and can be used with a wide range of output impedances. The ADL5354 provides two switched LO paths that can be used in time division duplex (TDD) applications where it is desirable to ping-pong between two local oscillators. LO current can be externally set using a resistor to minimize dc current Rev ...
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... ADL5354 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... Performance........................................................................... 4 3.3 V Performance........................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. Performance........................................................................... 7 3.3 V Performance...................................................................... 14 REVISION HISTORY 2/11—Revision 0: Initial Version Spur Tables ...................................................................................... Performance ...
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... LO Test Conditions/Comments Tunable to >20 dB over a limited bandwidth Differential impedance 200 MHz Externally generated Device enabled, IF output to 90% of its final level Device disabled, supply current < Device enabled Device disabled Rev Page ADL5354 Min Typ Max Unit Ω 2200 2700 MHz 230||0 ...
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... ADL5354 5 V PERFORMANCE 350 mA 25° 2535 MHz VGS0 = VGS1 = VGS2 = 0 V, and Ω, unless otherwise noted. O Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) ...
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... Exposure to absolute 6.0 V maximum rating conditions for extended periods may affect 5.5 V device reliability. 2.2 W 22°C/W ESD CAUTION 150°C −40°C to +85°C −65°C to +150°C 260°C Rev Page ADL5354 ...
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... LOSW 24, 25, 26 VGS0, VGS1, VGS2 27 LOI2 29 MNLG 31 MNLE 32, 33 MNOP, MNON 35 MNGM EPAD 1 MNIN MNCT 2 COMM 3 ADL5354 VPOS 4 COMM 5 TOP VIEW (Not to Scale) VPOS 6 COMM 7 DVCT 8 DVIN 9 NOTES CONNECT EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 2. Pin Configuration Description RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled. ...
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... Figure 6. Input IP2 vs. RF Frequency +85° –40° +25° 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 RF FREQUENCY (GHz) Figure 7. Input P1dB vs. RF Frequency +85° +25° –40° 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 RF FREQUENCY (GHz) Figure 8. SSB Noise Figure vs. RF Frequency ADL5354 2.65 2.70 2.65 2.70 2.65 2.70 ...
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... ADL5354 350 mA 25° 2535 MHz Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. O 400 390 380 V S 370 360 V 350 S 340 330 V S 320 310 300 –40 –30 –20 – TEMPERATURE (°C) Figure 9. Supply Current vs. Temperature 9 ...
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... T = +25° 130 180 230 280 330 IF FREQUENCY (MHz) Figure 19. Input P1dB vs. IF Frequency 130 180 230 280 330 IF FREQUENCY (MHz) Figure 20. SSB Noise Figure vs. IF Frequency ADL5354 380 430 380 430 380 430 ...
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... ADL5354 350 mA 25° 2535 MHz Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted –40° +25° +85° –6 –4 – POWER (dBm) Figure 21. Power Conversion Gain vs. LO Power ...
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... Rev Page RESISTANCE CAPACITANCE 80 130 180 230 280 330 380 IF FREQUENCY (MHz) 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 RF FREQUENCY (GHz) Figure 31. RF Return Loss, Fixed IF SELECTED UNSELECTED 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 LO FREQUENCY (GHz) Figure 32. LO Return Loss, Selected and Unselected ADL5354 430 2.65 2.70 2.45 2.50 ...
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... ADL5354 350 mA 25° 2535 MHz kΩ Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted –40° +85° +25° 2.20 2.25 2.30 2.35 2.40 2.45 2.50 RF FREQUENCY (GHz) Figure 33. LO Switch Isolation vs. RF Frequency – ...
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... BIAS RESISTOR VALUE (kΩ) INPUT IP3 SSB NOISE FIGURE CONVERSION GAIN 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 IF BIAS RESISTOR VALUE (kΩ) Resistor Value –40° +25° +85° 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 RF FREQUENCY (GHz) Figure 44. IF Channel-to-Channel Isolation vs. RF Frequency ADL5354 1.6 1.7 1 1.7 1.8 2.65 2.70 ...
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... ADL5354 3.3 V PERFORMANCE 200 mA 25° 2535 MHz and Ω, unless otherwise noted. O 208 206 204 T = –40°C A 202 200 198 T = +25°C A 196 194 T = +85°C 192 A 190 188 2.20 2.25 2.30 2.35 2.40 2.45 2.50 RF FREQUENCY (GHz) Figure 45. Supply Current vs. RF Frequency at 3 ...
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... Rev Page ADL5354 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 < ...
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... LOI1 LO SUBSYSTEM The ADL5354 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources ...
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... V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5354 has a power-down mode that permits the dc current to drop to ~300 μA. The logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1 ...
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... IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. MIXER VGS CONTROL DAC The ADL5354 features three logic control pins, VGS0 (Pin 24), VGS1 (Pin 25), and VGS2 (Pin26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands ...
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... L3 R4 VCC C24 C13 C12 C28 C20 C29 T2 DIV_OUTN C30 C31 R9 Figure 52. Typical Application Circuit Rev Page ADL5354 VCC C16 27 R12 R16 26 R7 C34 R13 25 R8 R14 R17 24 R11 R15 23 22 R19 21 VCC C26 ...
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... Evaluation board layout is shown in Figure 54 and Figure 55. R10 MAIN_OUTP C33 C32 T1 C19 C17 C27 C8 C21 C25 C18 VCC R1 C22 VCC L6 ADL5354 TOP VIEW (Not to Scale) L3 C23 R4 VCC VCC C24 C13 C12 C28 C20 C29 T2 DIV_OUTN C30 C31 R9 Figure 53 ...
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... R19, PWDN PWDN interface. When the PWDN 2-pin shunt is inserted, the ADL5354 is powered down. When R19 is open, it pulls the PWDN logic low and enables the device. The jumper can be removed to allow PWDN interface to be exercised using an external logic generator. Grounding the PWDN pin is allowed during nominal operation but is not permitted when supply voltages exceed 3 ...
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... ADL5354 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model ADL5354ACPZ-R2 ADL5354ACPZ-R7 ADL5354-EVALZ RoHS Compliant Part. 6.00 BSC SQ 0.60 MAX 27 0.50 BSC TOP 5.75 VIEW BSC SQ 0.75 19 0.60 0.50 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.35 0.08 0.20 REF 0.28 0.23 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1 Figure 56. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...
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... NOTES Rev Page ADL5354 ...
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... ADL5354 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09118-0-2/11(0) Rev Page ...