ADL5201-EVALZ AD [Analog Devices], ADL5201-EVALZ Datasheet
ADL5201-EVALZ
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ADL5201-EVALZ Summary of contents
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... SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN INTERFACE VPOS GND PWUP LOGIC 0dB TO 31.5dB 150Ω +20dB ADL5201 Figure 1. is powered on by applying the appropriate logic ADL5201 provides precise gain adjustment capabilities with www.analog.com ©2011 Analog Devices, Inc. All rights reserved. VOUT+ VOUT– ...
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... ADL5201 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Characterization and Test Circuits............................................... 14 Theory of Operation ...................................................................... 15 Digital Interface Overview ........................................................ 15 Parallel Digital Interface ............................................................ 15 Serial Peripheral Interface (SPI) ............................................... 15 Up/Down Interface ...
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... Gain code = 000000, high performance mode p-p OUT p-p OUT p-p composite OUT Gain code = 000000, high performance mode p-p OUT p-p OUT p-p composite OUT Rev Page ADL5201 Min Typ Max Unit 700 MHz 5.5 V/ns −18.73 dB −18.8 dB 10.8 V p-p 150 Ω 1.5 V 51.44 dB ...
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... ADL5201 Parameter POWER-UP INTERFACE Power-Up Threshold PWUP Input Bias Current GAIN CONTROL INTERFACE Maximum Input Bias Current SPI TIMING f SCLK POWER INTERFACE Supply Voltage Quiescent Current Power-Down Current TIMING DIAGRAMS t SCLK SCLK SDIO ...
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... V to −1.2 V section of this specification is not implied. Exposure to absolute 676.5 mW maximum rating conditions for extended periods may affect 37.16°C/W device reliability. 2.29°C/W 140°C –40°C to +85°C ESD CAUTION –65°C to +150°C 240°C Rev Page ADL5201 ...
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... Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V) enables low power mode. ADL5201 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PAD ...
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... MID GAIN (+5dB) MAX GAIN (+20dB 100 200 300 400 FREQUENCY (MHz –40° +25° +85° 100 150 200 250 300 FREQUENCY (MHz) ADL5201 8dB 6dB 5dB 7dB –10dB –11dB 1000 500 600 350 400 ...
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... ADL5201 60 –11.5dB 0dB +10dB 55 +20dB 100 150 200 250 FREQUENCY (MHz) Figure 12. Output Third-Order Intercept vs. Frequency at Four Gain Codes –40° +25° +85° 100 150 200 250 FREQUENCY (MHz) Figure 13. Output Third-Order Intercept vs. Frequency, Three Temperatures p-p Composite – ...
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... +25° +85° 100 150 200 250 300 FREQUENCY (MHz) Low Power Mode ADL5201 –40 –50 –60 –70 –80 –90 –100 –110 –120 –60 –70 –80 –90 –100 –110 –120 350 ...
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... ADL5201 60 –11.5dB 0dB +10dB 55 +20dB 100 150 200 250 FREQUENCY (MHz) Figure 24. Output Third-Order Intercept vs. Frequency at Four Gain Codes, Low Power Mode p-p Composite –40° +25° +85° 100 150 ...
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... P (dBm) OUT Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz, Three Temperatures, Low Power Mode CH1 200mV/DIV CH4 1V/DIV TIME (10ns/DIV) Figure 35. Disable Time Domain Response ADL5201 –40 –50 –60 –70 –80 –90 –100 –110 –120 –50 –60 – ...
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... ADL5201 CH2 500mV/DIV CH3 50mV/DIV TIME (10ns/DIV) Figure 36. Gain Step Time Domain Response 0 –10 –20 –30 –40 –50 –60 MAGNITUDE MAX GAIN –70 MAGNITUDE MIN GAIN PHASE MAX GAIN PHASE MIN GAIN –80 10 100 FREQUENCY (MHz) Figure 37. S11 Magnitude and Phase vs. Frequency 1 ...
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... GAIN CODE Figure 43. Phase Variation vs. Gain Code 0 –10 –20 –30 –40 –50 –60 1000 Rev Page 100 FREQUENCY (MHz) Figure 44. Disable-State Reverse Isolation vs. Frequency 10 100 FREQUENCY (MHz) Figure 45. Common-Mode Rejection Ratio vs. Frequency ADL5201 1000 1000 ...
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... TRACES 0.1µ + 1µH 1µ 0.1µF 0.1µF TC3-1T ADL5201 PAD LOSS = 11dB 0.1µF 0.1µ Figure 47. Test Circuit for Distortion, Gain, and Noise Figure 48. Differential-to-Differential Characterization Board Rev Page 0.1µF 50Ω ...
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... The step size is selectable using the GS1 and GS0 pins. The gain is limited by the top and bottom of the control range. DO NOT CARE (7 BITS) Table 6. Gain Step Size Control Truth Table READ/WRITE GS1 Rev Page ADL5201 FA0 Step Size (dB ...
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... DNC DNC DNC DNC LOGIC TIMING To write to the ADL5201, refer to the timing shown in Figure 51. The write mode uses a 16-bit serial word on the SDIO pin. The Voltage R/W bit of the word must be low to write Bits[D5:D0], which are Gain (dB) the binary weighted codes for the attenuation level (0 = minimum 4 3 ...
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... The linearity of the part, measured at the output, is first-order independent of the gain setting. From − +20 dB gain, the OIP3 is approximately 50 dBm into a 150 Ω load at 200 MHz (0 dBm per tone). At gain settings below −4 dB, the OIP3 drops to approximately 40 dBm. Rev Page ADL5201 ...
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... SOURCE R S 0.1µF 2 GAIN MODE INTERFACE MODE0 To enable the ADL5201, the PWUP pin must be pulled high (1.4 V ≤ PWUP ≤ 3.3 V). Taking PWUP low puts the in sleep mode, reducing current consumption to approximately ambient temperature. ADC DRIVING The ADL5201 is optimized for ADC interfacing. The output IMDs and noise floor remain constant throughout the 31 ...
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... V inductor voltage from the input common-mode voltage of the AD9467. The two 75 Ω resistors provide the 150 Ω load to the ADL5201, whose gain is load dependent. The 47 nH induc- tors and 14 pF capacitor constitute the (100 MHz − 1 dB) low-pass filter. The two 33 Ω isolation resistors suppress any switching currents from the ADC input sample-and-hold circuitry ...
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... In addition, the L6 inductor shorts the ADC inputs at dc, which introduces a zero into the transfer ADL5201 function. The ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. The final overall fre- quency response takes on a band-pass characteristic, helping to reject noise outside of the intended Nyquist zone ...
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... The ADL5201 evaluation board is configured with a USB-friendly interface to program the gain of the ADL5201. The software graphical user interface (see Figure 59) lets users select a particular gain mode and gain level to write to the device. The GUI also allows users to read back data from the SDIO pin, showing the currently programmed gain setting ...
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... ADL5201 SCHEMATICS AND ARTWORK PAD PAD GND_ZAP 4 VPOS_IG GND 1 VPOS_ID Figure 60. Evaluation Board Schematic Rev Page Data Sheet 09388-059 C17 ...
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... Data Sheet Figure 62. Top Layer Figure 61. Logic Schematic Figure 63. Bottom Layer Rev Page ADL5201 ...
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... R3 and installing a 0 Ω jumper at R4. R3, R4 R13 C1 provides dc blocking. R12 and R13 are placeholders and can be replaced with blocking capacitors when driving the ADL5201 from a fully differential source. R3 grounds one side of the differential drive interface for single-ended applications. R9, R10, and R11 are provided for generic placement of matching components ...
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... USB microcontroller (Cypress CY7C68013A-56LFXC) 64 kbit EEPROM (Microchip 24LC64-I/SN) Low dropout regulator (Analog Devices ADP3334ACPZ) 24 MHz crystal oscillator (AEL Crystals X24M000000S244) Rev Page ADL5201 ...
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... ADL5201 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADL5201ACPZ-R7 −40°C to +85°C ADL5201-EVALZ RoHS Compliant Part. 4.10 0.30 4.00 SQ 0.25 3.90 0.18 19 0.50 18 BSC EXPOSED PAD 13 12 0.50 TOP VIEW BOTTOM VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 64. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ × ...
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... Data Sheet NOTES Rev Page ADL5201 ...
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... ADL5201 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09388-0-10/11(0) Rev Page Data Sheet ...