ADL5201-EVALZ AD [Analog Devices], ADL5201-EVALZ Datasheet - Page 20

• Manufacturer Part Number: ADL5201-EVALZ
• Description: Wide Dynamic Range, High Speed
• Manufacturer: AD [Analog Devices]

ADL5201
An alternative narrow-band approach is presented in Figure 58.
By designing a narrow band-pass antialiasing filter between the
ADL5201
outside the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves by several decibels (dB) when a reasonable order
antialiasing filter is included. In this example, a low loss 1:3
input transformer is used to match the 150 Ω balanced input
of the
minimum insertion loss at the input.
Figure 58 shows the
the popular unbuffered Analog Devices ADCs: the AD9246,
AD9640, and AD6655. Table 8 includes antialiasing filter
component recommendations for popular IF sampling center
frequencies. Inductor L5 works in parallel with the on-chip
ADC input capacitance and a portion of the capacitance
presented by C4 to form a resonant tank circuit. The resonant tank
helps to ensure that the ADC input looks like a real resistance at
Table 8. Interface Filter Recommendations for Various IF Sampling Center Frequencies
Center Frequency
(MHz)
96
140
170
211
ADL5201
and the target ADC, the output noise of the
to a 50 Ω unbalanced source, resulting in
AC
50Ω
ADL5201
1 dB Bandwidth
(MHz)
27
31
25
40
1:3
optimized for driving some of
1nF
1nF
Figure 58. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications
ADL5201
INTERFACE
DIGITAL
L1 (nH)
68
47
39
30
5V
5V
5V
ADL5201
1µH
1µH
Rev. 0 | Page 20 of 28
1nF
1nF
C2 (pF)
15
11
10
7
L1
L1
C2
the target center frequency. In addition, the L6 inductor shorts
the ADC inputs at dc, which introduces a zero into the transfer
function. The ac coupling capacitors and the bias chokes introduce
additional zeros into the transfer function. The final overall fre-
quency response takes on a band-pass characteristic, helping to
reject noise outside of the intended Nyquist zone. Table 8 provides
initial suggestions for prototyping purposes. Some empirical
optimization may be needed to help compensate for actual PCB
parasitics.
LAYOUT CONSIDERATIONS
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
To minimize the parasitic capacitance, a good practice is to avoid
any ground or power planes under this routing region and under
the chokes.
L3
L3
C4
L3 (nH)
220
150
120
100
CML
L5
L5
75Ω
75Ω
C4 (pF)
15
11
10
7.5
L6
AD9246
AD9640
AD6655
L5 (nH)
68
47
47
30
Data Sheet
L6 (nH)
150
82
51
43