74lcxh16373 Fairchild Semiconductor, 74lcxh16373 Datasheet

74lcxh16373

Manufacturer Part Number

74lcxh16373

Description

Voltage 16-bit Transparent Latch With Bushold

Manufacturer

Fairchild Semiconductor

Datasheet

1.74LCXH16373.pdf (11 pages)

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74LCXH16373GX

(Note 1)

74LCXH16373MEA

(Note 2)

74LCXH16373MTD

(Note 2)

74LCXH16373

Low Voltage 16-Bit Transparent Latch with Bushold

General Description

The LCXH16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear transparent to the data when the Latch Enable (LE)

is HIGH. When LE is LOW, the data that meets the setup

time is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LCXH16373 is designed for low voltage (2.5V or 3.3V)

environment.

The LCXH16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

The LCXH16373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data input at a valid logic level.

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with capability of interfacing to a 5V signal

Package Number

(Preliminary)

BGA54A

MS48A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500440

Features

I 5V tolerant control inputs and outputs

I 2.3V–3.6V V

I 5.4 ns t

I Bushold on inputs eliminates the need for external

I Power down high impedance outputs

I ± 24 mA output drive (V

I Implements patented noise/EMI reduction circuitry

I Latch-up performance exceeds 500 mA

I ESD performance:

I Also available in plastic Fine-Pitch Ball Grid Array

pull-up/pull-down resistors

(FBGA) (Preliminary)

Human body model > 2000V

Machine model > 200V

Package Description

max (V

specifications provided

= 3.3V), 20 µ A I

= 3.0V)

February 2001

Revised August 2001

www.fairchildsemi.com

max

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74lcxh16373 Summary of contents

Page 1

... REEL] 74LCXH16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide (Note 2) 74LCXH16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Bushold Inputs ...

Page 3

Functional Description The LCXH16373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

DC Electrical Characteristics Symbol Parameter I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output Leakage OZ I Power-Off Leakage Current OFF I Quiescent Supply Current CC ∆I Increase in ...

Page 6

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL PLH Propagation Delay PHL PLH n t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ ...

Page 7

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Test PLH PZL t ,t PZH PHZ Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable ...

Page 8

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS48A 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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