hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 20

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hyb18t512160b2fl-5

Manufacturer Part Number
hyb18t512160b2fl-5
Description
512-mbit Double-data-rate-two Sdram
Manufacturer
Qimonda
Datasheet
3
This chapter contains the functional description.
3.1
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM.
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
Field
BA2
BA1
BA0
A13
PD
WR
DLL
Bits
16
15
14
13
12
[11:9]
8
Type
reg. addr.
w
w
w
Functional Description
Mode Register Set (MRS)
1)
Description
Bank Address 2
Note: BA2 not available on 256 Mbit and 512 Mbit components
0
Bank Address 1
0
Bank Address 0
0
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
Active Power-Down Mode Select
0
1
Write Recovery
Note: All other bit combinations are illegal.
001
010
011
100
101
DLL Reset
0
1
B
B
B
B
B
B
B
B
B
B
B
B
B
BA2 Bank Address
BA1 Bank Address
BA0 Bank Address
A13 Address bit 13
PD Fast exit
PD Slow exit
WR 2
WR 3
WR 4
WR 5
WR 6
DLL No
DLL Yes
2)
20
512-Mbit Double-Data-Rate-Two SDRAM
Mode Register Definition, BA
HY[B/I]18T512[40/80/16]0B2[C/F](L)
Internet Data Sheet
TABLE 11
2:0
= 000
B

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