dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 292

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Register 26-2:
DS70292C-page 290
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
R/W-0
BUSY
R-0
WAITB<1:0>
BUSY: Busy bit (Master mode only)
1 = Port is busy (not useful when the processor stall is active)
0 = Port is not busy
IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<10:0> by 1 every read/write cycle
01 = Increment ADDR<10:0> by 1 every read/write cycle
00 = No increment or decrement of address
MODE16: 8-Bit/16-Bit Mode bit
1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers
0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer
MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits
11 = Data wait of 4 T
10 = Data wait of 3 T
01 = Data wait of 2 T
00 = Data wait of 1 T
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 T
•
•
•
0001 = Wait of additional 1 T
0000 = No additional wait cycles (operation forced into one T
WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits
11 = Wait of 4 T
10 = Wait of 3 T
01 = Wait of 2 T
00 = Wait of 1 T
R/W-0
R/W-0
(1)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
PMMODE: PARALLEL PORT MODE REGISTER
IRQM<1:0>
W = Writable bit
‘1’ = Bit is set
CY
CY
CY
CY
R/W-0
R/W-0
CY
CY
CY
CY
; multiplexed address phase of 4 T
; multiplexed address phase of 3 T
; multiplexed address phase of 2 T
; multiplexed address phase of 1 T
CY
CY
R/W-0
R/W-0
Preliminary
WAITM<3:0>
INCM<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
CY
CY
CY
CY
MODE16
CY
R/W-0
R/W-0
)
(1)
(1)
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
WAITE<1:0>
MODE<1:0>
R/W-0
R/W-0
(1)
bit 8
bit 0