dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 4

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

System Management:
• Flexible clock options:
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
Audio Digital-to-Analog Converter (DAC):
• 16-bit Dual Channel DAC module
• 100 ksps maximum sampling rate
• Second-Order Digital Delta-Sigma Modulator
Data Converter Interface (DCI) module:
• Codec interface
• Supports I
• Up to 16-bit data words, up to 16 words per frame
• 4-word deep TX and RX buffers
Comparator Module:
• Two analog comparators with programmable
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
DS70292C-page 2
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
- Two and four simultaneous samples (10-bit ADC)
- Up to 13 input channels with auto-scanning
- Conversion start can be manual or
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
input/output configuration
synchronized with one of four trigger sources
2
S and AC’97 protocols
Preliminary
Communication Modules:
• 4-wire SPI (up to two modules):
• I
• UART (up to two modules):
• Enhanced CAN (ECAN™ module) 2.0B active:
• Parallel Master Slave Port (PMP/EPSP):
• Programmable Cyclic Redundancy Check (CRC):
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
- Framing supports I/O interface to simple
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
- Supports 8-bit or 16-bit data
- Supports 16 address lines
- Programmable bit length for the CRC
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
Note:
2
C™:
codecs
sampling modes
monitoring
Transmission Requests
generator polynomial (up to 16-bit length)
input
®
encoding and decoding in hardware
See the device variant tables for exact
peripheral features per device.
© 2009 Microchip Technology Inc.