at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 164

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

21.8.1
21.8.1.1
164
AT91SAM9G20 Preliminary
Read Waveforms
NRD Waveform
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
Figure 21-8. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
NBS0,NBS1,
NBS2,NBS3,
A0, A1
falling edge;
rising edge;
rising edge.
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
D[31:0]
A[25:2]
MCK
NRD
NCS
NCS_RD_SETUP
NRD_SETUP
Figure
21-8.
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NRD_HOLD
NCS_RD_HOLD
6384B–ATARM–15-Dec-08