at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 169

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

21.8.3.3
21.8.3.4
21.8.3.5
6384B–ATARM–15-Dec-08
Null Delay Setup and Hold
Null Pulse
Write Cycle
The write-cycle time is defined as the total duration of the write cycle, that is, from the time
where address is set on the address bus to the point where address may change. The total write
cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see
ever, for devices that perform write operations on the rising edge of NWE or NCS, such as
SRAM, either a setup or a hold must be programmed.
Figure 21-13. Null Setup and Hold Values of NCS and NWE in Write Cycle
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
NWR0, NWR1,
NWR2, NWR3
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A
D[31:0]
NWE,
[25:2]
MCK
NCS
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
AT91SAM9G20 Preliminary
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
Figure
21-13). How-
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