at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 796

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2
44.2.1
44.2.1.1
44.2.2
44.2.2.1
44.2.2.2
44.2.2.3
44.2.2.4
44.2.2.5
796
AT91SAM9G20 Errata - Revision “A” Parts
AT91SAM9G20 Preliminary
Analog-to-digital Converter (ADC)
MCI
ADC: Sleep Mode
MCI: Busy Signal of R1b responses is not taken in account
MCI: SDIO Interrupt does not work for slot different from A
MCI: Data Timeout Error Flag
MCI: Data Write Operation and number of bytes
MCI: Flag Reset is not correct in half duplex mode
Refer to
If Sleep mode is activated while there is no activity (no conversion is being performed), it will
take effect only after a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, in order put ADC into sleep mode at the end of this conversion.
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a
conflict can occur on data line0 if the MCI sends data to the card while the card is still busy.The
behavior is correct for CMD12 command (STOP_TRANSFER).
None.
If 1-bit data bus width and on other slots than slot A, the SDIO interrupt can not be captured. The
sample is made on the bad data line.
None
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled wait-
ing indefinitely the Data start bit.
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect. These flags are reset correctly after a PDC channel enable.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Section 44.1 “Marking” on page
795.
6384B–ATARM–15-Dec-08