Type
ROM ( 8-bit)
RAM ( 8-bit)
Package
Minimum Instruction
Execution Time
Interrupts
Timer Counter
Serial Interface
I/O Pins
A/D Inputs
MN102L360C
I/O
• RESET • Watchdog • Timer counter 0 to 5 • Fixed-length serial ch.0,1 transmission
• Fixed-length serial ch.0,1 reception • Timer counter 6 to 7 • Timer counter 6 to 7 compare capture A
• Timer counter 6 to 7 compare capture B • ATC transfer finish • External 0 to 7 • Serial ch.0,1 transmission
• Serial ch.0,1 reception • NMI pin • A/D conversion finish
Timer counter 0: 8-bit 1 (timer output, event count)
Timer counter 1: 8-bit 1 (timer output, even count, A/D conversion start)
Timer counter 2 to 3: 8-bit 1 (timer output, event count, UART baud rate generation)
Timer counter 4,5: 8-bit 1 (timer output, event count)
Timer counter 6, 7: 16-bit 2
Connectable
Serial 0: 7, 8-bit 1 (common use with UART, transfer direction of MSB/LSB selectable)
Serial 1: 7, 8-bit 1 (common use with UART, transfer direction of MSB/LSB selectable)
Fixed-length serial 0: 8-bit 1
Fixed-length serial 1: 8-bit 1
8-bit 8-ch. (with S/H)
83
(timer output, event count, input capture, output compare, PWM output, 2-phase encoder input)
• Common use: 8 (by 4 bits), 75 (by bit)
Clock source ····················· 1/1, 1/128 of system clock frequency; 1/4 of low speed clock frequency;
Interrupt source ················· timer counter 0 underflow
Clock source ····················· system clock; 1/4 of low speed clock frequency; external clock; timer counter 0 output
Interrupt source ················· timer counter 1 underflow
Clock source ····················· system clock; external clock; timer counter 0 output; timer counter 1, 2 output
Interrupt source ················· timer counter 2, 3 underflow
Clock source ····················· 1/4 of low speed clock frequency; external clock; timer counter 0 output;
Interrupt source ················· timer counter 4, 5 underflow
Clock source ····················· system clock; external clock; timer counter 4, 5 output
Interrupt source ················· coincidence with compare capture A or at capture; coincidence with compare
Clock source ····················· 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency; external
I
Clock source ····················· 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency; external
I
Clock source ····················· external clock
Sending direction ·············· LSB
Clock source ····················· external clock
Sending direction ·············· LSB
2
2
C mode (master transmission/reception is possible in the single master system.)
C mode (master transmission/reception is possible in the single master system.)
timer counter 0 to 5
external clock
timer counter 3, 4 output
capture B or at capture; underflow of timer counter 6, 7
clock; 1/2 of timer counter 2 frequency
clock; 1/2 of timer counter 3 frequency
100 ns (at 4.5 V to 5.5 V, 20 MHz)
LQFP128-P-1818C
MN102L360C
External
5 K
*Lead-free
MAE00008FEM