mb95fv100d-103 Fujitsu Microelectronics, Inc., mb95fv100d-103 Datasheet - Page 42

• Manufacturer Part Number: mb95fv100d-103
• Description: 8-bit Proprietary Microcontrollers
• Manufacturer: Fujitsu Microelectronics, Inc.

42
MB95100AM Series
(2) Source Clock/Machine Clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
*
Source clock*
division)
Source clock frequency
Machine clock*
execution time)
Machine clock
frequency
2
(Clock before setting
(Minimum instruction
: Operation clock of the microcontroller. Machine clock can be selected as follows.
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Parameter
1
2
Sym-
t
t
F
F
bol
F
F
SCLK
MCLK
MPL
SPL
MP
SP
name
Pin





16.384
0.031
1.024
61.5
0.50
61.5
Min
7.6
7.6
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, T
Value
Typ








131.072 kHz When using sub clock
131.072 kHz When using sub clock
16.250 MHz When using main clock
32000
16.25
976.5
2000
Max
61.0
MHz When using main clock
Unit
µs
µs
ns
ns
When using main clock
Min : F
Max : F
When using sub clock
Min : F
Max : F
When using main clock
Min : F
Max : F
When using sub clock
Min : F
Max : F
SP
SPL
PLL multiplied by 1
SP
SPL
CL
CL
CH
CH
= 16.25 MHz, no division
= 0.5 MHz, divided by 16
= 131 kHz, no division
= 16 kHz, divided by 16
= 32 kHz, PLL multiplied by 4
= 32 kHz, divided by 2
= 16.25 MHz,
= 1 MHz, divided by 2
Remarks
A
= − 40 °C to + 85 °C)