cop87l88rg National Semiconductor Corporation, cop87l88rg Datasheet - Page 18

• Manufacturer Part Number: cop87l88rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

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UART
ETDX TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2 it is selected by setting ETDX bit
To simulate line break generation software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers
STP78 This bit is set to program the last Stop bit to be
7 8th of a bit in length
STP2 This bit programs the number of Stop bits to be trans-
mitted
STP2
STP2
Associated I O Pins
Data is transmitted on the TDX pin and received on the RDX
pin TDX is the alternate function assigned to Port L pin L2
it is selected by setting ETDX (in the ENUI register) to one
RDX is an inherent function of Port L pin L3 requiring no
setup
The baud rate clock for the UART can be generated on-
chip or can be taken from an external source Port L pin L1
(CKX) is the external clock I O pin The CKX pin can be
either an input or an output as determined by Port L Config-
uration and Data registers (Bit 1) As an input it accepts a
clock signal which may be selected to drive the transmitter
and or receiver As an output it presents the internal Baud
Rate Generator output
UART Operation
The UART has two modes of operation asynchronous
mode and synchronous mode
ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero The input frequency to the UART is 16
times the baud rate
The TSFT and TBUF registers double-buffer data for trans-
mission While TSFT is shifting out the current character on
the TDX pin the TBUF register may be loaded by software
with the next byte to be transmitted When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register There is also the
XMTG bit which is set to indicate that the UART is transmit-
ting This bit gets reset at the end of the last frame (end of
last Stop bit) TBUF is a read write register
The RSFT and RBUF registers double-buffer data being re-
ceived The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit Upon sensing this low level it waits for half a bit
time and samples again If the RDX pin is still low the re-
ceiver considers this to be a valid Start bit and the remain-
ing bits in the character frame are each sampled a single
time at the mid-bit position Serial data input on the RDX pin
is shifted into the RSFT register Upon receiving the com-
plete character the contents of the RSFT register are cop-
ied into the RBUF register and the Received Buffer Full Flag
(RBFL) is set RBFL is automatically reset when software
reads the character from the RBUF register RBUF is a read
only register There is also the RCVG bit which is set high
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0
1
(Continued)
One Stop bit transmitted
Two Stop bits transmitted
18
13) The format is selected using control bits in the ENU
when a framing error occurs and goes low once RDX goes
high TBMT XMTG RBFL and RCVG are read only bits
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the
clock Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock
This mode is selected by setting SSEL bit in the ENUI regis-
ter The input frequency to the UART is the same as the
baud rate
When an external clock input is selected at the CKX pin
data transmit and receive are performed synchronously with
this clock through TDX RDX pins
If data transmit and receive are selected with the CKX pin
as clock output the device generates the synchronous
clock output at the CKX pin The internal baud rate genera-
tor is used to produce the synchronous clock Data transmit
and receive are performed synchronously with this clock
FRAMING FORMATS
The UART supports several serial framing formats (Figure
ENUR and ENUI registers
The first format (1 1a 1b 1c) for data transmission (CHL0
cluding parity) and 7 8 one or two Stop bits In applications
using parity the parity bit is generated and verified by hard-
ware
The second format (CHL0
Start bit eight Data bits (excluding parity) and 7 8 one or
two Stop bits Parity bit is generated and verified by hard-
ware
The third format for transmission (CHL0
consists of one Start bit nine Data bits and 7 8 one or two
Stop bits This format also supports the UART ‘‘ATTEN-
TION’’ feature When operating in this format all eight bits
of TBUF and RBUF are used for data The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR registers called XBIT9 and RBIT9 RBIT9 is a read
only bit Parity is not generated or verified in this mode
For any of the above framing formats the last Stop bit can
be programmed to be 7 8th of a bit in length If two Stop
bits are selected and the 7 8th bit is set (selected) the
second Stop bit will be 7 8th of a bit in length
The parity is enabled disabled by PEN bit located in the
ENU register Parity is selected for 7- and 8-bit modes only
If parity is enabled (PEN
performed by PSEL0 and PSEL1 bits located in the ENU
register
Note that the XBIT9 PSEL0 bit located in the ENU register
serves two mutually exclusive functions This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame There is no parity selection in
this framing format For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with
PSEL1 to select parity
The frame formats for the receiver differ from the transmit-
ter in the number of Stop bits required The receiver only
requires one Stop bit in a frame regardless of the setting of
the Stop bit selection bits in the control register Note that
an implicit assumption is made for full duplex UART opera-
tion that the framing formats are the same for the transmit-
ter and receiver
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1 CHL1
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0) consists of Start bit seven Data bits (ex-
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1) the parity selection is then
0 CHL1
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0) consists of one
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0 CHL1
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1)