cop87l88rg National Semiconductor Corporation, cop87l88rg Datasheet - Page 7

• Manufacturer Part Number: cop87l88rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R C clock option) the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below Reading the G6 and
G7 data bits will return zeros
Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE PLUS to operate with the alter-
nate phase of the SK clock The G7 configuration bit if set
high enables the clock start up delay after HALT when the
R C clock configuration is used
Port G has the following alternate features
Port G has the following dedicated functions
Port C is an 8-bit I O port The 40-pin device does not have
a full complement of Port C pins The unavailable pins are
not terminated A read operation for these unterminated
pins will return unpredictable values
PORT I is an eight-bit Hi-Z input port
Port I1–I3 are used for Comparator 1 Port I4–I6 are used
for Comparator 2
The Port I has the following alternate features
Port D is a recreated 8-bit output port that is preset high
when RESET goes low D port recreation is one clock cycle
behind normal port timing The user can tie two or more D
port outputs (except D2) together in order to get a higher
drive
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
G1 WDOUT WATCHDOG and or Clock Monitor dedicat-
G7 CKO Oscillator dedicated output or general purpose
I1
I2
I3
I4
I5
I6
G7
G6
ed output
input
COMP1
COMP1
COMP1OUT (Comparator 1 Output)
COMP2
COMP2
COMP2OUT (Comparator 2 Output)
b
a
b
a
IN (Comparator 1 Negative Input)
IN (Comparator 2 Negative Input)
IN (Comparator 1 Positive Input)
IN (Comparator 2 Positive Input)
CLKDLY
Alternate SK
Config Reg
(Continued)
Data Reg
HALT
IDLE
7
Functional Description
The architecture of the device is modified Harvard architec-
ture With the Harvard architecture the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM) Both ROM and RAM have their own separate
addressing space with separate address buses The archi-
tecture though based on Harvard architecture permits
transfer of data from ROM to RAM
CPU REGISTERS
The CPU can do an 8-bit addition subtraction logical or
shift operation in one instruction (t
There are six CPU registers
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer which can be optionally
post auto incremented or decremented
X is an 8-bit alternate RAM address pointer which can be
optionally post auto incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
interrupt stack (in RAM) The SP is initialized to RAM ad-
dress 06F with reset
S is the 8-bit Data Segment Address Register used to ex-
tend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC)
PROGRAM MEMORY
The program memory consists of 32 kbytes of OTP
EPROM These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction jump vectors
for the JID instruction and interrupt vectors for the VIS in-
struction) The program memory is addressed by the 15-bit
program counter (PC) All interrupts in the devices vector to
program memory location 0FF Hex
The device can be configured to inhibit external reads of the
program memory This is done by programming the Security
Byte
Note Mask ROMed devices with equivalent on-chip features and program
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range This
byte can be addressed only from programming mode by a
programmer tool
Security is an optional feature and can only be asserted
after the memory array has been programmed and verified
A secured part will read all 00(hex) by a programmer The
part will fail Blank Check and will fail Verify operations A
Read operaiton will fill the programmer’s memory with
00(hex) The Security Byte itself is always readable with val-
ue of 00(hex) if unsecure and FF(hex) if secure
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers the I O registers (Configuration Data
and Pin) the control registers the MICROWIRE PLUS SIO
shift register and the various registers and counters asso-
ciated with the timers (with the exception of the IDLE timer)
Data memory is addressed directly by the instruction or indi-
rectly by the B X SP pointers and S register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
memory sizes of 4k 8k 16k 20k and 24k are available
c
) cycle time
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