cop87l84rg National Semiconductor Corporation, cop87l84rg Datasheet - Page 23

• Manufacturer Part Number: cop87l84rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

Interrupts
At this time since GIE
disabled The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions The user would then pro-
gram a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching
Thus if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS then the
interrupt with the higher rank will override any lower ones
and will be acknowledged The lower priority interrupt(s) are
still pending however and will cause another interrupt im-
mediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serv-
iced This lower priority interrupt will occur immediately fol-
lowing the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed
Inside the interrupt service routine the associated pending
bit has to be cleared by software The RETI (Return from
Interrupt) instruction at the end of the interrupt service rou-
tine will set the GIE (Global Interrupt Enable) bit allowing
the processor to be interrupted again if another interrupt is
active and pending
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank
The addresses of the different interrupt service routines
called vectors are chosen by the user and stored in ROM in
a table starting at 01E0 (assuming that VIS is located be-
tween 00FF and 01DF) The vectors are 15-bit wide and
therefore occupy 2 ROM locations
(Continued)
e
0 other maskable interrupts are
FIGURE 16 Interrupt Block Diagram
23
Figure 16 shows the Interrupt block diagram
VIS and the vector table must be located in the same
256-byte block (0y00 to 0yFF) except if VIS is located at the
last address of a block In this case the table must be in the
next block The vector table cannot be inserted in the first
256-byte block (y
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte)
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF
If by accident a VIS gets executed and no interrupt is ac-
tive then the PC (Program Counter) will branch to a vector
located at 0yE0– 0yE1
A Default VIS interrupt handler routine must be present As
a minimum this handler should confirm that the GIE bit is
cleared (this indicates that the interrupt sequence has been
taken) take care of any required housekeeping restore
context and return Some sort of Warm Restart procedure
should be implemented These events can occur without
any error on the part of the system designer or programmer
Note There is always the possibility of an interrupt occurring during an
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped
instruction which is attempting to reset the GIE bit or any other inter-
rupt enable bit If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit the interrupt enable bit will be
reset but an interrupt may still occur This is because interrupt pro-
cessing is started at the same time as the interrupt bit is being reset
To avoid this scenario the user should always use a two three or
four cycle instruction to reset interrupt enable bits
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WARNING
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