cop8acc National Semiconductor Corporation, cop8acc Datasheet - Page 18

• Manufacturer Part Number: cop8acc
• Description: 8-bit Cmos Rom Based And Otp Microcontrollers With 4k Or 16k Memory And High Resolution A/d
• Manufacturer: National Semiconductor Corporation

www.national.com
Power Save Modes
However, the clock monitor circuitry, if enabled, remains
active and will cause the WATCHDOG output pin (WDOUT)
to go low. If the HALT mode is used and the user does not
want to activate the WDOUT pin, the Clock Monitor should
be disabled after the devices come out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
devices are minimal and the applied voltage (V
decreased to V
machine.
The devices support three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the Port L.
The second method is with a low to high transition on the
CKO (G7) pin. This method precludes the use of the crystal
clock configuration (since CKO becomes a dedicated out-
put), and so may only be used with an RC clock configura-
tion. The third method of exiting the HALT mode is by pulling
the RESET pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to
generate a fixed delay to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid Wakeup signal, only the
oscillator circuitry is enabled. The IDLE timer is loaded with
a value of 256 and is clocked with the t
clock. The t
down by a factor of 10. The Schmitt trigger following the CKI
inverter on the chip ensures that the IDLE timer is clocked
only when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed to
the rest of the chip.
If an RC clock option is being used, the fixed delay is
introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be
introduced or not. The delay is included if CLKDLY is set,
and excluded if CLKDLY is reset. The CLKDLY bit is cleared
on reset.
The devices have two mask options associated with the
HALT mode. The first mask option enables the HALT mode
feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the devices
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the devices cannot be placed
in the HALT mode (writing a “1” to the HALT flag will have no
effect, the HALT flag will remain “0”).
IDLE MODE
In the IDLE mode, program execution stops and power
consumption is reduced to a very low level as with the HALT
mode. However, the on-board oscillator, IDLE Timer (Timer
T0), and Clock Monitor continue to operate, allowing real
time to be maintained. The devices remain idle for a selected
amount of time up to 65,536 instruction cycles, or 65.536
milliseconds with a 1 MHz instruction clock frequency, and
then automatically exits the IDLE mode and returns to nor-
mal program execution.
C
clock is derived by dividing the oscillator clock
r
(V
r
= 2.0V) without altering the state of the
(Continued)
C
instruction cycle
CC
) may be
18
The devices are placed in the IDLE mode under software
control by setting the IDLE bit (bit 6 of the Port G data
register).
The IDLE timer window is selectable from one of five values,
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this
value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to
keep track of elapsed time in the IDLE state. The IDLE timer
runs continuously at the instruction clock rate, whether or not
the devices are in the IDLE mode. Each time the bit of the
timer associated with the selected window toggles, the
T0PND bit is set, an interrupt is generated (if enabled), and
the devices exit the IDLE mode if in that mode. If the IDLE
timer interrupt is enabled, the interrupt is serviced before
execution of the main program resumes. (However, the in-
struction which was started as the part entered the IDLE
mode is completed before the interrupt is serviced. This
instruction should be a NOP which should follow the enter
IDLE instruction.) The user must reset the IDLE timer pend-
ing flag (T0PND) before entering the IDLE mode.
As with the HALT mode, these devices can also be returned
to normal operation with a reset, or with a Multi-Input
Wakeup input. Upon reset the ITMR register is cleared and
the ITMR register selects the 4,096 instruction cycle tap of
the Idle Timer.
The IDLE timer cannot be started or stopped under software
control, and it is not memory mapped, so it cannot be read or
written by the software. Its state upon Reset is unknown.
Therefore, if the devices are put into the IDLE mode at an
arbitrary time, it will stay in the IDLE mode for somewhere
between 1 and the selected number of instruction cycles.
In order to precisely time the duration of the IDLE state, entry
into the IDLE mode must be synchronized to the state of the
IDLE Timer. The best way to do this is to use the IDLE Timer
interrupt, which occurs on every underflow of the bit of the
IDLE Timer which is associated with the selected window.
Another method is to poll the state of the IDLE Timer pending
bit T0PND, which is set on the same occurrence. The Idle
Timer interrupt is enabled by setting bit T0EN in the ICNTRL
register.
Any time the IDLE Timer window length is changed there is
the possibility of generating a spurious IDLE Timer interrupt
by setting the T0PND bit. The user is advised to disable
IDLE Timer interrupts prior to changing the value of the
ITSEL bits of the ITMR Register and then clear the TOPND
bit before attempting to synchronize operation to the IDLE
Timer.
Note: As with the HALT mode, it is necessary to program two NOP’s to allow
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers section.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the devices from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 4 edge selectable external interrupts.
Figure 12 shows the Multi-Input Wakeup logic.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the devices to exit the HALT or IDLE modes.
The selection is done through the register WKEN. The reg-
clock resynchronization upon return from the IDLE mode. The NOP’s
are placed either at the beginning of the IDLE timer interrupt routine or
immediately following the “enter IDLE mode” instruction.