cop8acc National Semiconductor Corporation, cop8acc Datasheet - Page 30

• Manufacturer Part Number: cop8acc
• Description: 8-bit Cmos Rom Based And Otp Microcontrollers With 4k Or 16k Memory And High Resolution A/d
• Manufacturer: National Semiconductor Corporation

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MICROWIRE/PLUS
Where t
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The devices may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 18 shows how
two devices, microcontrollers and several peripherals may
be
arrangements.
WARNING
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SIO register. SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
TABLE 9. MICROWIRE/PLUS Master Mode Clock Select
FIGURE 17. MICROWIRE/PLUS Block Diagram
interconnected
SL1
0
0
1
C
is the instruction cycle clock
using
SL0
0
1
x
(Continued)
the
MICROWIRE/PLUS
SK period
2 X t
4 X t
8 X t
C
C
C
DS012865-63
30
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table 10 summarizes the bit settings
required for Master mode of operation.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table XI summarizes the settings required to enter
the Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated.
Alternate SK Phase Operation
The devices allow either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock.
In the alternate SK phase operation, data is shifted in on the
falling edge of the SK clock and shifted out on the rising edge
of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configu-
ration bit. The SKSEL flag will power up in the reset condi-
tion, selecting the normal SK signal.
This table assumes that the control flag MSEL is set.
Config. Bit
G4 (SO)
TABLE 10. MICROWIRE/PLUS Mode Settings
1
0
1
0
Config. Bit
G5 (SK)
1
1
0
0
STATE
STATE
Fun.
TRI-
TRI-
G4
SO
SO
Fun.
Ext.
Ext.
G5
Int.
SK
Int.
SK
SK
SK
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Slave
MICROWIRE/PLUS
Slave
Operation