cop888eb National Semiconductor Corporation, cop888eb Datasheet - Page 25

• Manufacturer Part Number: cop888eb
• Description: 8-bit Cmos Rom Based Microcontrollers With 8k Memory, Can Interface, 8-bit A/d, And Usart
• Manufacturer: National Semiconductor Corporation

Functional Block Description of
the CAN Interface
REGISTER DATA LENGTH CODE AND IDENTIFIERLOW
REGISTER (RIDL)(Address X’00A6)
This register is read only.
RID3..RID0 Receive Identifier bits (lower four bits)
The RID3..RID0 bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches
the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-
cepted if the Receive Identifier Acceptance Filter (RIAF) bit is
set to zero.
RDLC3..RDLC0 Receive Data Length Code bits
The RDLC3..RDLC0 bits determine the number of data
bytes within a received frame.
RECEIVE IDENTIFIER HIGH (RID)(Address X’00A7)
This register is read/write.
Bit 7 is reserved and should be zero.
RID10..RID4 Receive Identifier bits (upper bits)
The RID10...RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. If the Receive Identifier Acceptance
Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to
10 of the received identifier are compared with the mask bits
of RID4..RID10. If the corresponding bits match, the mes-
sage is accepted. If the RIAF bit is set to a one, the filter
function is disabled and all messages, independent of iden-
tifier, will be accepted.
CAN PRESCALER REGISTER (CSCAL)(Address
X’00A8)
This register is read/write.
CKS7..0 Prescaler divider select.
The resulting clock value is the CAN Prescaler clock.
CAN BUS TIMING REGISTER (CTIM) (Address X’00A9)
This register is read/write.
PPS2..PPS0 Propagation Segment, bits 2..0
The PPS2..PPS0 bits determine the length of the propaga-
tion delay in Prescaler clock cycles (PSC) per bit time. (For
a more detailed discussion of propagation delay and phase
segments, see SYNCHRONIZATION.)
PS2..PS0 Phase Segment 1, bits 2..0
The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The
PS2..PS0 bits also set the synchronization Jump Width to a
value equal to the lesser of: 4 PSC, or the length of PS1/2
(Min: 4 l length of PS1/2).
Bits 1 and 0 are reserved and should be zero.
RID3
Bit 7
Reserved
CKS7
PPS2
Bit 7
Bit 7
Bit 7
RID2
PPS1
CKS6
RID10
RID1
PPS0
CKS5
RID9
RID0
PS2
CKS4
RID8
RDLC3
PS1
(Continued)
CKS3
RID7
PS0
RDLC2
CKS2
RID6
Reserved
RDLC1
CKS1
RID5
Reserved
RDLC0
Bit 0
Bit 0
CKS0
RID4
Bit 0
Bit 0
25
LENGTH OF TIME SEGMENTS (See Figure 28 )
Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
CAN BUS CONTROL REGISTER (CBUS) (00AA)
Reserved These bits are reserved and should be zero.
RIAF
If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
the RIAF bit is set to a one, the filter function is disabled and
all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
Bus synchronization of the device is done in the following
way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received. Resetting the TxEN1
and TxEN0 bits will disable the output drivers and the CAN
input comparator. All other CAN related registers and flags
will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
• The Synchronization Segment is 1 CAN Prescaler clock
• The Propagation Segment can be programmed (PPS) to
• Phase Segment 1 and Phase Segment 2 are program-
served
PS2
Bit 7
Re-
TxEN1
0
0
0
0
1
1
1
1
(PSC)
be 1,2...,8 PSC in length.
mable (PS) to be 1,2,..,8 PSC long.
the rx-pins through the receive comparator (worst case assumption: 3
clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz
CKI and CSCAL = 0.
0
0
1
1
RIAF
TABLE 5. Synchronization Jump Width
PS1
0
0
1
1
0
0
1
1
Receive identifier acceptance filter bit
TxEN1
TxEN0
TABLE 6. Output Drivers
PS0
0
1
0
1
0
1
0
1
0
1
0
1
TxEN0
Segment
Length of
Tx0, Tx1 TRI-STATE, CAN
input comparator disabled
Tx0 enabled
Tx1 enabled
Tx0 and Tx1 enabled
Phase
1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
RxREF1
can
can
can
can
can
can
can
can
1
⁄
2
RxREF0
Output
Synchronization
Jump Width
served
1 t
2 t
3 t
4 t
4 t
4 t
4 t
4 t
Re-
www.national.com
can
can
can
can
can
can
can
can
FMOD
Bit 0