cop888eb National Semiconductor Corporation, cop888eb Datasheet - Page 46

• Manufacturer Part Number: cop888eb
• Description: 8-bit Cmos Rom Based Microcontrollers With 8k Memory, Can Interface, 8-bit A/d, And Usart
• Manufacturer: National Semiconductor Corporation

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MICROWIRE/PLUS
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuraiton register. Table 12 summarizes the bit settings
required for Master or Slave mode of operation.
Where t
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and re-
setting the appropriate bit in the Port G configuration regis-
ter. Table 3 summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Salve mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated.
TABLE 11. MICROWIRE/PLUS Master Mode
SL1
c
0
0
1
is the instruction cycle clock
Clock Selection
SL0
0
1
x
(Continued)
FIGURE 35. MICROWIRE/PLUS Application
2 X t
4 X t
8 X t
SK
c
c
c
46
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock in
the normal mode. In the alternate SK phase mode the SIO
register is shifted on the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
This table assumes that the control flag MSEL is set.
Config.
(SO)
G4
Bit
1
0
1
0
TABLE 12. MICROWIRE/PLUS Mode Selection
Config.
(SK)
G5
Bit
1
1
0
0
TRI-STATE
TRI-STATE
Fun.
SO
SO
G4
DS012837-37
Ext. SK
Ext. SK
Int. SK
Int. SK
Fun.
G5
MICROWIRE/
PLUS Master
MICROWIRE/
PLUS Master
MICROWIRE/
MICROWIRE/
PLUS Slave
PLUS Slave
Operation