cop8fg National Semiconductor Corporation, cop8fg Datasheet - Page 14

• Manufacturer Part Number: cop8fg
• Description: 8-bit Cmos Rom Based And Otp Microcontrollers With 8k To 32k Memory, Two Comparators And Usart
• Manufacturer: National Semiconductor Corporation

www.national.com
5.0 Functional Description
Memory address ranges 0200 to 027F and 0300 to 037F are
unavailable on the COP8FGx5 and, if read, will return under-
fined data.
5.5 ECON (CONFIGURATION) REGISTER
For compatibility with COP8FGx7 devices, mask options are
defined by an ECON Configuration Register which is pro-
grammed at the same time as the program code. Therefore,
the register is programmed at the same time as the program
memory.
The format of the ECON register is as follows:
Bit 7
Bit 6
Bit 5
Bits 4, 3 = 0, 0 External CKI option selected. G7 is avail-
Bit 2
Bit 1
Bit 0
5.6 USER STORAGE SPACE IN EPROM
The ECON register is outside of the normal address range of
the ROM and can not be accessed by the executing soft-
ware.
The COP8 assembler defines a special ROM section type,
CONF, into which the ECON may be coded. Both ECON and
User Data are programmed automatically by programmers
that are certified by National.
The following examples illustrate the declaration of ECON
and the User information.
Bit 7
X
= 0
= 0
= 0
= 0
= x
= 1
= 1
= 1
= 1
= 1
Bit 6
POR
= 0, 1 R/C oscillator option selected. G7 is avail-
= 1, 0 Crystal oscillator with on-chip crystal bias
= 1, 1 Crystal oscillator with on-chip crystal bias
SECURITY
Bit 5
This is for factory test. The polarity is “Don’t
Care.”
Power-on reset enabled.
Power-on reset disabled.
Security enabled.
able as a HALT restart and/or general pur-
pose input. CKI is clock input.
able as a HALT restart and/or general pur-
pose input. CKI clock input. Internal R/C
components are supplied for maximum R/C
frequency.
resistor disabled. G7 (CKO) is the clock
generator output to crystal/resonator.
resistor enabled. G7 (CKO) is the clock
generator output to crystal/resonator.
WATCHDOG feature disabled. G1 is a gen-
eral purpose I/O.
WATCHDOG feature enabled. G1 pin is
WATCHDOG output with weak pullup.
Force port I compatibility. Disable port F
outputs and pull-ups. This is intended for
compatibility with existing code and Mask
ROMMed devices only. This bit should be
programmed to 0 for all other applications.
Enable full port F capability.
HALT mode disabled.
HALT mode enabled.
CKI 2
Bit 4
CKI 1
Bit 3
WATCH
DOG
Bit 2
(Continued)
F-Port
Bit 1
HALT
Bit 0
14
Syntax:
[label:] .sect
Example: The following sets a value in the ECON register
and User Identification for a COP8FGR728M7. The ECON
bit values shown select options: Power-on enabled, Security
disabled, Crystal oscillator with on-chip bias disabled,
WATCHDOG enabled and HALT mode enabled.
5.7 RESET
The devices are initialized when the RESET pin is pulled low
or the On-chip Power-On Reset is enabled.
The following occurs upon initialization:
.sect
.db
.db
.endsect
Port L: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T2CNTRL: CLEARED
T3CNTRL: CLEARED
Accumulator, Timer 1, Timer 2 and Timer 3:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
econ, conf
0x55
'my v1.00' ;user data declaration
.db
.db
.endsect
FIGURE 9. Reset Logic
econ, conf
value
<user information>
;por, xtal, wd, halt
; up to 8 bytes
;1 byte,
;configures options
DS101116-13