cop8fg National Semiconductor Corporation, cop8fg Datasheet - Page 45

• Manufacturer Part Number: cop8fg
• Description: 8-bit Cmos Rom Based And Otp Microcontrollers With 8k To 32k Memory, Two Comparators And Usart
• Manufacturer: National Semiconductor Corporation

14.0 Instruction Set
Example: Load Accumulator Immediate
Immediate Short. This is a special case of an immediate in-
struction. In the “Load B immediate” instruction, the 4-bit im-
mediate value in the instruction is loaded into the lower
nibble of the B register. The upper nibble of the B register is
reset to 0000 binary.
Example: Load B Register Immediate Short
Indirect from Program Memory. This is a special case of
an indirect instruction that allows access to data tables
stored in program memory. In the “Load Accumulator Indi-
rect” (LAID) instruction, the upper and lower bytes of the Pro-
gram Counter (PCU and PCL) are used temporarily as a
pointer to program memory. For purposes of accessing pro-
gram memory, the contents of the Accumulator and PCL are
exchanged. The data pointed to by the Program Counter is
loaded into the Accumulator, and simultaneously, the original
contents of PCL are restored so that the program can re-
sume normal execution.
Example: Load Accumulator Indirect
14.3.2 Tranfer-of-Control Addressing Modes
Program instructions are usually executed in sequential or-
der. However, Jump instructions can be used to change the
normal execution sequence. Several transfer-of-control ad-
dressing modes are available to specify jump addresses.
A change in program flow requires a non-incremental
change in the Program Counter contents. The Program
Counter consists of two bytes, designated the upper byte
(PCU) and lower byte (PCL). The most significant bit of PCU
is not used, leaving 15 bits to address the program memory.
Different addressing modes are used to specify the new ad-
dress for the Program Counter. The choice of addressing
mode depends primarily on the distance of the jump. Farther
jumps sometimes require more instruction bytes in order to
completely specify the new Program Counter contents.
LD A, # 05
LD B, # 7
LAID
Memory Location
Accumulator
Reg/Data
041F Hex
Accumulator
Memory
Reg/Data
Memory
Reg/Data
B Pointer
PCU
Memory
PCL
(Continued)
Contents
Contents
Contents
XX Hex
12 Hex
04 Hex
35 Hex
1F Hex
25 Hex
Before
Before
Before
Contents
Contents
Contents
05 Hex
07 Hex
04 Hex
36 Hex
25 Hex
25 Hex
After
After
After
45
The available transfer-of-control addressing modes are:
• Jump Relative
• Jump Absolute
• Jump Absolute Long
• Jump Indirect
The transfer-of-control addressing modes are described be-
low. Each description includes an example of a Jump in-
struction using a particular addressing mode, and the effect
on the Program Counter bytes of executing that instruction.
Jump Relative. In this 1-byte instruction, six bits of the in-
struction opcode specify the distance of the jump from the
current program memory location. The distance of the jump
can range from −31 to +32. A JP+1 instruction is not allowed.
The programmer should use a NOP instead.
Example: Jump Relative
Jump Absolute. In this 2-byte instruction, 12 bits of the in-
struction opcode specify the new contents of the Program
Counter. The upper three bits of the Program Counter re-
main unchanged, restricting the new Program Counter ad-
dress to the same 4 kbyte address space as the current in-
struction.
(This restriction is relevant only in devices using more than
one 4 kbyte program memory space.)
Example: Jump Absolute
Jump Absolute Long. In this 3-byte instruction, 15 bits of
the instruction opcode specify the new contents of the Pro-
gram Counter.
Example: Jump Absolute Long
JP 0A
JMP 0125
JMP 03625
Memory
Reg/
PCU
PCL
PCU
PCU
Reg
PCL
Reg
PCL
Contents
Contents
Contents
0C Hex
Before
02 Hex
05 Hex
Before
77 Hex
Before
42 Hex
36 Hex
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Contents
Contents
Contents
0F Hex
02 Hex
01 Hex
25 Hex
36 Hex
25 Hex
After
After
After